282 questions
2
votes
1
answer
61
views
compilation issues with sc_dt::sc_biguint data types (systemc)
I'm facing an compilation issues with sc_dt::sc_biguint data types. I tried to reproduce the issue with a simple example below
#include<iostream>
#include<systemc.h>
using namespace std;
...
- 49
0
votes
1
answer
185
views
Driving sc_signal using sc_in, sc_out using sc_signal
Given a wrapper module with some exports (sc_in, sc_out)
I would like to drive multiple core module sc_in signals and allow multiple core modules to drive sc_out signals of the wrapper (one driver per ...
- 311
1
vote
1
answer
47
views
SystemC-AMS: Initialization for tracing of: v_supercap failed set wave to 0
I receive the error in the title when I simulate my supercapacitor class with systemC. More precisely, the whole error message is as follows:
Warning: SystemC-AMS: Initialization for tracing of: ...
0
votes
1
answer
487
views
SystemC Error with wait() in SC_THREAD: "wait() is only allowed in SC_THREADs and SC_CTHREADs"
I'm working on a convolutional neural network simulation using SystemC for a school homework. My code includes a module Conv2d with an SC_THREAD for the forward pass of a convolutional layer, which ...
0
votes
1
answer
107
views
systemc: how to detect two events happen at the same time
I am using systemc to model a packet-based network. There are two parallel threads, which process random size packet. After each packet, I'd like to check whether the other thread happens to be in the ...
- 307
0
votes
1
answer
171
views
How to define `sc_fixed` variables that have word/integer lengths that are based off (but not the same size as!) those of a template parameter
Let's say I want to write a generic SystemC module which does some algorithm processing on fixed point data of various representations, so I implement it as as module template where the fixed point ...
- 35
0
votes
0
answers
40
views
error: declaration of 'class T' template <class T> class FIFO_READ_HS: public sc_module, public sc_fifo_in_if<T>
Coming accross declaration of 'class T' error.
I have this code:
#include "systemc.h"
template <class T> class FIFO_READ_HS: public sc_module, public sc_fifo_in_if<T>
{
...
-1
votes
1
answer
389
views
SystemC on MAC m1 with Vscode: Undefined symbols for architecture arm64
I am building systemC environment in Mac m1. I finished the whole process of systemC build and check and installation. All example cases passed in command line.
However, when I tried to integrate the ...
- 307
-1
votes
1
answer
109
views
I'm trying to simulate 3 LED's with 2 switches using systemc
With 2 switches s1,s2 and 3 Lights l1 l2 l3. pressing s1 or s2 should switch on l1. Next step if I press s1, l1(off) and l2(on) or if I press s2, l1(off) and l3(on). Final state is on press of any ...
- 71
4
votes
2
answers
1k
views
makefile.in not found while installing systemC
I'm trying to install SystemC on mac (x86, macOs 13.0.1). I followed the steps described in the docs:
$ cd path/to/systemc-2.3.3
$ mkdir objdir
$ cd objdir
$ export CXX=g++
$ ../configure
But when I ...
- 181
-1
votes
1
answer
138
views
How to determine which port has invoked an sc_thread if the thread is sensitive to multiple ports in SystemC?
I have a thread which is sensitive to an array of ports.
In this thread I want to find out which port had triggered this thread so that i can read the value of that port?
Is there a way to determine ...
- 1
1
vote
2
answers
196
views
Makefile:77: *** missing separator. Stop
Hi I am trying to install systemC on WSL2, when I run sudo make I seem to be getting this error
Making all in src
make[1]: Entering directory '/home/ryans/systemc-2.3.4/src'
Makefile:77: *** missing ...
- 496
2
votes
2
answers
350
views
what the meaning of (a&b)>>c in this systemc code? [duplicate]
when I read SYSTEMC code,I find a function return int like this:
static inline int rp_get_busaccess_response(struct rp_pkt *pkt)
{
return (pkt->busaccess_ext_base.attributes & ...
- 25
-1
votes
1
answer
153
views
How to simulate output delay using sc_method but without using next_trigger() in SystemC?
SC_MODULE(example) {
sc_in < int > a, b;
sc_in < int > out
Void process() {
// Output delay implement here
}
SC_CTOR(example) {
SC_METHOD(process);
...
- 1
1
vote
0
answers
416
views
What API to use for a Verilator test harness?
Verilator can output SystemC or C++ classes. There is a 'Verilator' API and I can find the headers, but they are just raw classes with no documentation. Some code looks like classes that are used ...
- 22.7k
0
votes
2
answers
253
views
How to dynamically create templated classes with compile-time information?
I am working on a small design with SystemC for a systolic array. For that I have implemented a templated shift register class where the data type and the delay are the templates. For every row of the ...
- 81
0
votes
1
answer
89
views
SystemC ERROR: type name requires a specifier or qualifier
I am trying to write synthesizable SystemC code.
My code:
struct test:sc_module{
sc_in<sc_lv<4>> inp;
sc_out<sc_lv<4>> outp;
void run(){
sc_lv<4> ...
- 1
0
votes
1
answer
246
views
Building SystemC Library for ISO C++ 2011 standard with MinGW
I have some C++ code, which requires the ISO C++ 2011 standard and also uses SystemC functionality.
Therefore I guess it makes most sense to build the SystemC library with the same standard.
For the ...
- 11
0
votes
1
answer
340
views
'b_transport' is not a member of 'tlm_utils::simple_initiator_socket<...>' while trying to use TLM2
I am trying to use TLM2 for a simulation project but for some reason I can't use b_transport the same way I see it used in other projects, here is the code snippet that doesn't build due to this error(...
- 1
1
vote
1
answer
82
views
SystemC simulation misses the first iteration
I'm having difficulties with initiating the simulation.
Whenever I start a for loop, I always miss the first iteration of the loop.
Here is my code:
#include <systemc.h>
#include <iostream>...
- 13
1
vote
1
answer
829
views
Error E109 - complete binding failed: port not bound
I have been to create a proof of concept for an instance inside an instance, and I am getting a "complete binding error", which I have not been able to get past. I have searched online, and ...
- 99
-3
votes
1
answer
793
views
How to integrate Eclipse, systemc-2.3.3, and cygwin on Windows? [closed]
How to integrate Eclipse, systemc-2.3.3, and cygwin on Windows?
- 1
1
vote
2
answers
1k
views
Cross-compiling SystemC libraries and linking to them
I'm starting from scratch and am following the main steps below:
1. Build and install a cross-compiler toolchain (host Linux, target Win64):
Get this MXE version, only changing plugins/gcc6/gcc6-...
- 167
1
vote
1
answer
281
views
Setting signals length using received parameters in SystemC
context
I'm making a simulation environment with systemC co-simulated with verilog/VHDL RTL modules using modelsim/questasim
My Verilog modules use parameters to set up each module
My VHDL modules use ...
- 147
4
votes
1
answer
933
views
How to simulate output delay using next_trigger() in SystemC?
I have been reading this upvoted answer on Stack Overflow: https://stackoverflow.com/a/26129960/12311164
It says that replacing wait(delay, units); in SC_THREAD to next_trigger(delay, units) in ...
user12311164
0
votes
1
answer
546
views
SystemC binding a socket to a port
I have a virtual model given to me by one of the vendors. This model has a port for interrupt and I want to connect it to my interrupt controller.
The problem is that the port in my interrupt ...
-1
votes
1
answer
263
views
Error: (E107) bind interface to port failed: type mismatch on port 4 of module `simple_instance.data_in_reg'
i want to read bus in register_out and write to bus in register_in but i get type mismatch error on port4 of register_in
Register.hpp file
#pragma once
#include<systemc.h>
#include"bus.hpp&...
1
vote
2
answers
543
views
typedef an sc_fixed but got template error
Trying to define a simple sc_fixed type in Visual Studio 2017:
#include <systemc.h>
#include <sysc/datatypes/fx/sc_fixed.h> # just in case
....
typedef sc_fixed<16, 4> fixed_type;
....
- 163
4
votes
2
answers
3k
views
Difference between sc_port and sc_export
Can someone clearly and intuitively explain what is the difference between an sc_port and an sc_export in SystemC? When does one use a port, and when an export?
I've been reading portions of the ...
- 599
0
votes
1
answer
407
views
Link issue on Windows with pthreads - Is gcc or SystemC to blame?
Hi,
I've recently come across a link issue that I cannot explain.
Here is an example that couldn't really be simpler:
sc_main.cpp:
#include <systemc.h>
int sc_main (int argc, char* argv[])
{
...
- 167
0
votes
0
answers
2k
views
Is there a way to create an array(or vector) of sc_out signal in a System C module?
I would like to create an array of sc_out and sc_in in sc_module. I looked at the documentation of sc_vector, but I couldn't get it to work. I like to be able to read and write individual sc_out port.
...
-3
votes
1
answer
182
views
How can fix Access Noxim installation Error
Plz Help what is the error when I run the "make"
g++ -g -O3 -I. -I.. -I../src -I/usr/local/systemc-2.3.2/include/systemc-2.2 -c ../src/NoximNoC.cpp
../src/NoximNoC.cpp:14:10: fatal error: ...
1
vote
0
answers
208
views
TLM-2.0 and SystemC-2.3.3 version
I followed the Doulos tutorial for the development of a simple bus-based master/slave communication system. My problem is that my code compiles perfectly with version 2.3.2 of SystemC but when I ...
0
votes
1
answer
173
views
Need help to implement an interrupt controller simulator which handles the ISR
I am on the implementation of an interrupt controller simulator, which will take signals from other rest of the HW modules in simulation and run the ISR.
Below is the SystemC code roughly made to get ...
- 1
0
votes
1
answer
1k
views
what is the the difference between Dataflow model and RTL style coding in verilog/SystemC
I have studied in my school that both the models are used in same perspective but when i went through online there are pages which define some tips to convert Dataflow models to RTL models, so can ...
- 17
0
votes
3
answers
3k
views
What is the Hardware synthesized for << operator
I have recently started working on HDL , while going through right/left shift operators what i have studied in my school was they are continous D FlipFlops that shift data bit by bit to result the ...
2
votes
1
answer
998
views
Is there a better/alternate way to implement delay in SystemC Modules
I have implemented a 4 bit adder with delay in its output port.
SC_MODULE(adder4){
sc_in<sc_uint<4>> A,B;
sc_out<sc_uint<4>> OUT;
sc_event ev;
sc_uint<4> ...
- 21
0
votes
1
answer
648
views
Member of b object can't write in SystemC
I got this error on SystemC, and I don't understand why. The error is:
'write': is not a member of
'sc_core::sc_in' ConsoleApplication1
'write': is not a member of 'sc_core::sc_in'
class "...
0
votes
1
answer
196
views
I got error to set up systemC2.3.3 with visual studio 2017
as I stated in the title I got a problem on setting up systemC on my windows pc. So I followed exactly step by step from this link Installing SystemC for VS2013 yet still fail. So I compile my error ...
0
votes
1
answer
1k
views
SC_METHOD in custom constructor
In my custom constructor i want to use SC_METHOD:
class host_command : public sc_module, public bus_if {
public:
// sc_out<packet_type> out_packet;
sc_buffer<packet_type> out_packet;
...
- 2,562
1
vote
1
answer
347
views
Prevent SC_METHOD from executing without event/trigger
My method fsm1 executes once even without event and therefore id1_cmd.read() and id1_value.read() contain 0 and not the correct values.
//--------------------------------------------------------------...
- 2,562
0
votes
1
answer
411
views
Error: (E112) get interface failed: port is not bound: port 'server.outgoin1' (sc_out)
I can't seem to figure out why I am getting the error.
server.cpp
#include "systemc.h"
SC_MODULE(server){
sc_in<bool> begin1, begin2, begin3, end1, end2, end3, incoming1, incoming2, ...
- 471
0
votes
1
answer
984
views
Why am I getting a segmentation fault (core dumped) in systemC?
I can't figure out why I'm getting segmentation fault in systemC. I have no clue why I'm getting those errors. Maybe it has something to do with how I'm calling the functions? The server has three ...
- 471
0
votes
1
answer
121
views
can't understand systemc '<<' operation
im looking 'risc-cpu' code which is in systemc library(specifically 'example' folder) but i can't understand what << operation in main.cpp is.
in main.cpp they instantiate each module and do &...
- 9
0
votes
2
answers
81
views
SystemC cannot use "+" "-" operators in visual studio 2019
enter image description here
I am trying to build the counter, when the "dec1" signal is high, the 8-bit unsign integer counter will decrese by 1. I am using visual sidio 2019 to complie the counter....
- 1
-1
votes
1
answer
2k
views
SystemC undefined Symbol for architecture x86_64
I'm trying to run SystemC on XCode on mac (using the standard Clang compiler). Depending on the language dialect, I get different error messages. If I use C++14, I get the error
No member named '...
- 2,109
0
votes
1
answer
172
views
Delay in bitvector Output assignment
I am a beginner in SystemC, and I really need your help in solving a timing issue.
Please find the stimuli.h code below,
SC_MODULE(datagen)
{
public:
sc_out<sc_bv<8>> ...
- 11
0
votes
1
answer
148
views
Automatic warning on fixed point overflow in SystemC
Is there a way i can enable an automatic warning for my SystemC simulation whenever a fixed point variable overflows?
I already discovered the overflow_flag() function, but that one have to be check ...
- 87
0
votes
1
answer
3k
views
Is it possible to bind the output of a submodule to two different output ports?
I am trying to make a circuit which computes the carries for an addition.
In this piece of code, I would like to connect the output port rOut of the submodule pg to two output ports (rOut and carries[...
- 15
0
votes
1
answer
215
views
Is there a simple systemc channel with a blocking write and read function?
I'm looking for a simple channel to use in system-c between sc_modules for the purpose of hardware modelling.
The functionality I'm looking for is basically an sc_fifo with size 0.
A write should be ...
