6,394 questions
0
votes
0
answers
54
views
Verilog & Vivado - How to load memory initialization files into BRAM on post-synthesis simulations
I am designing a 16 bit microcontroller for a college project using Vivado and Verilog. On behavioral simulations i use $readmemh and everything runs fine, the instructions are loaded from memory and ...
2
votes
2
answers
82
views
Proper way of resetting a FSM
I usually work with Xilinx FPGA boards. Based on the documentation I've reviewed and the research I've done, I try to avoid using a global reset signal in my designs as much as possible. However, let'...
- 21
2
votes
1
answer
82
views
Not seeing one-cycle delay for register in Modelsim
My register doesn't work properly. The output changes simultaneously with the input. There should be a one-cycle delay, but I am not seeing it from the simulation in Modelsim. Does anyone know why?
...
- 61
2
votes
1
answer
86
views
Why is my simple ARM7 data memory on Verilog failing tests?
I'm implementing a simple ARM7 in Verilog and am currently in the process of creating a simple data memory. I've come up with something like this:
// very simple sdata implementation with 1mb~ memory
...
- 301
1
vote
1
answer
121
views
Random stability with non-random object
I have a simple example for random stability in QuestaSim.
module sv_rand_stability;
class dummy;
rand int data;
endclass
initial begin
dummy d;
$display("%...
-1
votes
1
answer
89
views
`$display` output wrong result when caculate `-3*3`?
module te(
input a
);
reg clk;
reg [1:0]d1=2'd3;
reg signed [2:0]d2=-3'd3;
reg signed [4:0]d3;
always @(posedge clk) begin
d3<=d1*d2;
$display("%b",d3);//01111,how to know the ...
- 2,513
0
votes
0
answers
94
views
Ostensibly incorrect synthesis by SynplifyPro, result differs from Icarus Verilog & Verilator
I stumbled upon perplexing hardware behavior in the following simple circuit, provided here verbatim:
/// Given an WIN-bit signed input, truncates the most significant bits to produce a WOUT-bit ...
- 1,318
0
votes
0
answers
44
views
`ERROR: [VRFC 10-4982]` and `ERROR: [VRFC 10-8885]` through instantiation [duplicate]
`timescale 1ns/1ps
module ctrl(
output d0,
output reg d1,
output reg res=1'b1,
output reg d3,
output reg d4
);
reg [7:0] oper_cnt=8'd0;
reg clk;
assign d0=clk;
always @(...
- 2,513
4
votes
1
answer
117
views
How can I simulate a simple elevator FSM where it can detect overweight?
I've been doing a finite state machine of an elevator using Verilog. The elevator contains four states:
IDLE: When the elevator is stopped.
ERROR: When the elevator's weight limit is exceeded.
MOVING:...
- 71
-1
votes
1
answer
105
views
How to swap inout wires within a contained hierarchy (of which is synthesizable)?
For context, please look at my attached diagram to see what I am trying to accomplish.
Essentially, I want to swap inout wires using a contained hierarchy that will allow me to have more modular RTL ...
- 181
-1
votes
1
answer
73
views
Is `x==1'bx` in Verilog?
In Verilog, $display("%b",^ 3'b10x); outputs x.
As x==1'dx, I believe ^ 3'b10x==1'bx is true, but the result is false.
What's the correct result of ^ 3'b10x?
And why is ^ 3'b10x==1'bx false?
- 2,513
-3
votes
1
answer
166
views
`ERROR: [VRFC 10-2063] Module <my_task> not found while processing module instance <'Undefined'>` when using verilog task [closed]
`timescale 1ns/1ps
module m_top
(
input GCLK,
input [7:0] i_in1,
output o_out1,
output reg o_out2,
inout io_data,
output reg[7:0]yy
);
assign o_out1=5;
initial o_out2=6;
task my_task;
input a,b;
...
- 2,513
0
votes
1
answer
80
views
How to print array value in VerilogHDL?
`timescale 1ns/1ps
module m_top
(
input GCLK,//100MHz,Y9
input [7:0] i_in1,
output o_out1,
output reg o_out2,
inout io_data
);
reg hh [2:0][1:0] ;
reg [2:0]hh2[1:0] ;
always @(negedge GCLK)begin
...
- 2,513
-1
votes
1
answer
73
views
How to print the correct value of a signed reg variable?
`timescale 1ns/1ps
module a(
input a,
output [7:0]tmp
);
reg signed[2:0] m;
reg [2:0] n;
initial begin
m=4;
n=4;
$display("%f",m);//-4.000000
$display("%f",n);//4.000000
end
...
- 2,513
-4
votes
1
answer
203
views
Why is `-3'd300>5000` true in Verilog? [duplicate]
`timescale 1ns / 1ps
module m_top
(
input GCLK,//100MHz,Y9
output reg o_out2,
inout io_data
);
initial begin
if(-3'd300>5000)begin
$display("%b",-3'd300);//...
- 2,513
-6
votes
1
answer
97
views
`ERROR: [VRFC 10-2951] 'xxxx' is not a constant` when use verilog case function
`timescale 1ns / 1ps
module m_top
(
input GCLK,
output o_out2,
inout io_data
);
reg [2:0] compare;
case(compare)
3'd1:begin
assign o_out2=1;
end
3'd2:begin
assign o_out2=2;
end
default:begin
...
- 2,513
1
vote
1
answer
109
views
Is it possible to verilate and compile big generate with verilator?
I'm designing game of life in Verilog. The design consist of simple cell that been generated in grid with generate.
gol_cell.v :
module gol_cell (
input clk,
input rst,
input [...
- 3,901
2
votes
1
answer
82
views
Usage of assign: when to put it in an always or not [duplicate]
I know a lot of people have asked about when to use assign inside always, but I'm wondering if you actually have to. Is it ok to have a module where you have assign statements, but they are not inside ...
- 21
2
votes
2
answers
169
views
In Vivado, what is "[Synth 8-7213] Expression condition using operand 'x' does not match with the corresponding edges used in event control" error?
When I am doing some development with Verilog and Vivado, I wrote some Verilog code as follows:
module min_rep_example_A(input clk, input rst_n, output reg[3:0] LED);
always @(posedge clk or ...
- 78
0
votes
0
answers
71
views
Why does module instantiation affect output reg value in vivado? [duplicate]
The instantiation module as below:
module second_module(
input [7:0] d,
output reg [7:0] q
);
initial
q <= ~d;
endmodule
The top module as below:
module top_module(
input [7:0] ...
- 2,513
0
votes
1
answer
88
views
`$strobe` and `$display` output different result for the same target
Refer to this question,I write a similar case.
module n;
reg [1:0]a, b;
initial begin
a=1;
a<=a+1;
$strobe("strobe",a);
$display("display",a);
end
endmodule
The ...
- 2,513
1
vote
1
answer
80
views
Why `$monitor` output assignment result before time step?
module n;
reg [1:0]a, b;
initial begin
$monitor($time,," monitor ",a);
a=1;
a<=a+1;
#1;//assignment should happen here
end
endmodule
The expect output is:
1 monitor 2
but I got
0 ...
- 2,513
0
votes
1
answer
61
views
`$display` cannot display right value in vivado
`timescale 1ns / 1ps
module factorial(
input i_n,
output reg res,
input i_clk
);
integer j;
initial
begin:a
for (j=1;j<=i_n;j=j+1)begin
res<=res*j;
end
res<='d3;
$display("res is ...
- 2,513
3
votes
1
answer
114
views
The simulation results of Vivado are inconsistent with those of HDLBits
I studied Verilog and do my exercises on HDLBits. I came up with a question when trying to solve this problem: https://hdlbits.01xz.net/wiki/Exams/2014_q3fsm
I wrote the following codes according to ...
- 53
-1
votes
1
answer
110
views
How to run iterations through a module instance without using generate in Verilog
I'm a complete beginner when it comes to Verilog.
I have a block ROM which is as follows:
module CDbram_2_0_32 (clk, en, addr, dout);
input clk;
input en;
input [9:0] addr;
output [9:0] dout [0:37];
(...
1
vote
2
answers
126
views
Confusion about nonblocking assignments to signals for synchronous logic
I have Verilog code like this:
module gen_bits(input clk, input clear, input ld, input in, output reg[7:0] out);
always @(posedge clk) begin
if (clear)
out <= 8'b00000000;
...
- 53
-1
votes
1
answer
72
views
yosys - Get rid of `\` in synthesized module names
Consider the following example:
// example.v
module submod (
output logic sub_output
);
assign sub_output = 1'b1;
endmodule
module top;
logic out;
submod gen_submod ();
assign out ...
- 195
2
votes
1
answer
75
views
Getting a Verilog define value on the Python side using Cocotb
I'm trying to parse all Verilog defines I have in a specific file in my Verilog code. I.e. scan through definitions like the following:
`define A 3
`define B 5
`define C (A+B)
And translate it to a ...
- 31
-2
votes
1
answer
106
views
Can a verilog function return more than one value?
I am asking about standard Verilog 2001 and not System Verilog extensions.
I was sure it was listed as an advantage of tasks, over a function. However, I have this syntax working and it seems to at ...
- 22.7k
0
votes
0
answers
57
views
Problem with Tilelink protocol handshake between Rocket Core and a MMIO device
I am trying to add a MMIO device to rocket-chip in chipyard and I want to use Tilelink interface. This MMIO device is intended to be a slave and the rocket-core as the master. For this, I created a ...
- 182
1
vote
1
answer
93
views
System Verilog equivalent of VHDL's "wait until rising_edge() for ..." followed by "if rising_edge()"
I'm looking for SV code that is equivalent to these lines in VHDL:
process begin
wait until rising_edge(mysig) for 1 us;
if rising_edge(mysig) do_something() else do_something_else(); end if;
...
- 940
0
votes
2
answers
154
views
Generating a PWM signal in Verilog (Quartus Prime Lite)
I'm trying to generate a pulse width modulated signal to control the power with duty cycle, but don't know where I went wrong
This is the verilog code
module pwm_generator (
input wire clk, ...
- 73
-1
votes
1
answer
131
views
`get_ports *` cannot find port,deliver `WARNING: [Vivado 12-584]`
Sample verilog script as below:
`timescale 1ns/1ps
module Save_Mult_Df(Abar,Bbar,Cbar);
input Abar;
output Bbar;//Bbar is here
input Cbar;
assign Bbar=Abar+Cbar;
endmodule
module test();
reg Abar,...
- 2,513
1
vote
1
answer
74
views
Unexpected Waveform Behavior During RAM Data Transfer
I currently need to read 128 8-bit data. After reading 128 data, they are combined into a 1024-bit RAM which is then assigned to dout. The ram_cnt will count from 0 to 65535. When it counts 128 (0~...
- 27
-1
votes
1
answer
177
views
How to use `get_nets` to find `wire` in Vivado when get Vivado 12-1023 warning?
Verilog script as below:
`timescale 1ns/1ps
module Save_Mult_Df(A);
input A;
wire C;
assign C=A;
endmodule
module test();
reg A;
wire C;//should wire be added to testbench?
initial
A= 2'b10;
...
- 2,513
1
vote
2
answers
85
views
Is there a formal statement in the IEEE SystemVerilog standard that temporary variables can be used in procedural blocks?
I wrote a module which used the writing method like:
always_ff@(posedge clk)begin
logic [WIDTH-1:0] signal1;
........
end
When I compiled it in VCS, I drove the signal in testbench, and when I ...
- 13
1
vote
1
answer
807
views
RAM array displays 'XXXXX'
Purpose: Input 128 data, store them in RAM, and output them to dout after collecting 128 data.
di is an input variable. RAM is used to store 128 data. When RAM collects 128 numbers, dout will write ...
- 13
3
votes
1
answer
122
views
Verilog full adder
This is the Verilog question. I have written the code according to the image, but I'm getting mismatch in the output, can I get some assistance?
module add1 ( input a, input b, input cin, output ...
- 73
1
vote
1
answer
99
views
How to get my 4:1 multiplexer outputs right when implementing a function?
I've been assigned to create a 4:1 multiplexer in Verilog, and then implement the function:
F(X, Y, Z) = (X*Y') + (Y'*Z') + (X'*Z')
If I did the everything right on paper, the s0 = Y, s1 = Z, I0 = 0, ...
- 11
1
vote
1
answer
82
views
No expected result when using Vivado. What's the problem with the testbench file?
I tried to reproduce loadable counter in Vivado 2023.1, but I cannot get expected result.
My testbench file is below:
`timescale 1ns / 1ps
module behav_counter();
reg [7:0] d;
reg clk;
reg ...
- 2,513
1
vote
1
answer
94
views
In a testbench, is there a way to see the internal declared regs/wires of a module without having to connect them to ports?
Let's say we're trying to write a Verilog/SystemVerilog testbench code named SC_TB for module sample_code. Is there a more practical way of seeing what reg B and wire Cw is doing in testbench, without ...
- 13
1
vote
1
answer
67
views
How to Fix “Net Cannot Be Assigned More Than One Value” Error When Using Multiple SPI Modules? [closed]
I'm working on a Verilog project for the DE10-Lite FPGA board that interfaces with a 3-axis accelerometer over SPI. I have separate SPI modules (spi_ee_config) for each axis: x_info, y_info, and ...
1
vote
1
answer
214
views
Vivado bi-directional INOUT signal on non-top-module
I've recently started working with bi-directional data transfer.
I wrote a simple Verilog module that takes an input in one clock cycle and returns a processed result (by adding one) after the bus ...
- 758
2
votes
1
answer
76
views
How do SystemVerilog VPI applications schedule in the Re-Active regions?
The SystemVerilog spec describes a scheduler model in Figure 4-1 (p. 67 of IEEE 1800-2023). It describes a number of regions, including an Active region set and a Re-Active region set.
Orthogonally, ...
- 53
2
votes
2
answers
109
views
What are the differences between using hierarchical names and port declarations?
In Verilog, you can declare wires/registers
as ports and connect them at instantiation (port_A in example)
as ports and connect them "later"/"outside" using hierarchical names (...
- 4,313
1
vote
1
answer
64
views
Use different clocks in the property from the sample clock
I need to write a property to check the divisor of a fast clock. I’ve tried the following options:
property clk_frequency_P(logic pll_clk, logic destination_clk, logic clk_en, logic reset, int divisor)...
- 153
1
vote
1
answer
328
views
Why is my waveform not showing on Vivado?
module DCP_21(
input a,
input b,
output w,
output x,
output y,
output z
);
assign w = ~(a & b);
assign x = ~(a | b);
assign y = a^b;
assign z = ~(...
- 11
1
vote
1
answer
100
views
Using Quartus IP Catalog, how can I get predefined module name and ports order?
For the code below, I utilized a predefined RAM module from Quartus to create the RAM. How do I determine the port order when instantiating it?
I understand it must be compatible with the module from ...
- 11
0
votes
1
answer
180
views
CocoTB: How to test interaction between two Verilog modules
What is a good way to test the interaction between two (or more) modules using cocotb?
For example, say we have a transmitter (TX) and receiver (RX) module, and we want to test them together (e.g., RX ...
- 29
4
votes
2
answers
147
views
Issue with driving an LED matrix using an FPGA (Verilog)
I am trying to run an LED matrix using an FPGA. The specifics are a TinyFPGA BX, wired into this board (driver chip datasheet), connected to this screen. Before this, I managed to drive this matrix ...
- 43