5,813 questions
-1
votes
1
answer
122
views
Difference between signal and variable in VHDL (FPGA hardware perspective, not just simulation)
I understand the usual textbook difference between signal and variable in VHDL:
variable := updates immediately inside a process
signal <= updates after a delta cycle
variables are local, ...
1
vote
1
answer
105
views
attribute of generic type in vhdl
I am trying to write a generic function in vhdl for converting from vector to array.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package test is
type slv_arr is ...
- 303
3
votes
1
answer
158
views
Slice direction of unconstrained std_logic_vector
I have a component with unconstrained std_logic_vector (ADDRA : in std_logic_vector). When I use this in a port map, I did this ADDRA(9 downto 0) => DpSysAddrTrunc(9 downto 0). I'm using Lattice, ...
- 312
1
vote
1
answer
85
views
VHDL float32 error, what are suitable values for the float32 type?
Assigning to the float32 type produces the error below
in questa 2024.3 on eda playground.
** Error: testbench.vhd(9): Real literal 0 is not of type ieee.float_pkg.float32.
** Error: testbench.vhd(14):...
- 2,620
-1
votes
3
answers
258
views
Are these two VHDL processes synchronous?
How should I create a slow clock derived from a (possibly much) faster clock without creating a gated clock, and while maintaining 50% duty cycle on slow_clk? In the code below the input port clk is ...
- 21
-1
votes
2
answers
126
views
convert a VHDL string to an integer ascii equivalent
Suppose I have VHDL code that has a generic string STACK with the value "top". I want to pass it to a SystemVerilog module as a parameter, but SV does not have a type compatible with VHDL ...
- 1
3
votes
2
answers
98
views
How to handle procedure overloads of signals in VHDL-2008 [closed]
I have a general question regarding the calling of procedures with other types. In the general sense, what is the correct way to declare an overload of a procedure so it may be called later using ...
- 131
6
votes
1
answer
119
views
Deallocating after returning line using std.textio ieee library
A known problem in VHDL is that using parts of a return statement (e.g to_string(slv(i))'length) will generate a warning/error on compile. To work around an unknown string length, I tried using the ...
- 131
2
votes
2
answers
221
views
Efficient 16-bit std_logic_vector comparator in VHDL
I'm working on a VHDL project where I need to implement a comparator between two 16-bit std_logic_vector signals, a and b. The goal is to check if a is greater than, less than, or equal to b.
The ...
- 21
2
votes
0
answers
86
views
Quartus Prime flexible RAM ip component
In Quartus II it was possible to make a flexible RAM component with a little "generic" modification to a SINGLE file generated by MegaWizzard manager. So it was so easy and fast to add ...
0
votes
1
answer
115
views
Shifter's vectors (VHDL) stay undefined in Modelsim . What is wrong?
Sadly, stack wont let me post an image yet...so,for uni i have to recreate a circuit in vhdl code, but when i run it simulate it in Modelsim, all vectors (except input_vector) remain undefined. I get ...
- 17
0
votes
0
answers
122
views
How to simulate a Xilinx IP using Cocotb makefile?
I have a VHDL design that includes the Xilinx FFT IP, and I am using cocotb with Aldec Riviera for the simulation.
In the cocotb makefile, I insert all my vhdl source files (including the .vhd file of ...
- 81
3
votes
1
answer
140
views
instantiating generic package in VHDL with a few constraints
I want to instantiante a generic package so that it's visible to an entity such that
a generic to the entity is passed as a generic to the package
one of the port types of the entity is defined in ...
- 133
0
votes
1
answer
95
views
Can a function return a sub-type
Can a function return a sub-type, e.g.:
function foo() return signed(15 down 0) is ...
It doesn't works on the Xilinx compiler I'm using, but return signed (no sub-type) does.
However I don't know if ...
- 1,040
-2
votes
2
answers
117
views
Why do i need to use rising_edge in this VHDL code? [duplicate]
so what is the difference between these two vhdl programs:
process(clk)
begin
if(clk=1)
q<=d;
end if;end process;
and this one:
process(clk)
begin
if(rising_edge clk)
q<=d;
end if;end ...
- 11
1
vote
1
answer
164
views
vhdl can't determine type of object
The code below produces -
Error (10327): VHDL error at XXXX.vhd(1581): can't determine definition of operator ""&"" -- found 47 possible definitions
Error (10647): VHDL type ...
- 127
0
votes
0
answers
54
views
m_axis_result_tvalid is not asserting during floating point operation
I'm trying to do some operations in a Xilinx FPGA. Here is my code. When i simulate the code, the error validation signal does not assert. i need the signal to allow the next step of operations to ...
- 11
0
votes
0
answers
107
views
LCOV reporting branch coverage for non-branch lines in VHDL code - bug or expected behavior?
I'm working with GHDL (GHDL - v6.0.0-dev - Ubuntu 24.04 (x86-64, LTS) - gcc backend) and LCOV to analyze code coverage for VHDL projects, but I'm encountering unexpected behavior in the branch ...
1
vote
1
answer
125
views
In VHDL does a signal passing through a port incur a delta cycle delay?
I know that in VHDL signal assignments incur a delta-cycle of delay, meaning that if I have:
bar <= foo;
bar will update one delta cycle after foo changes. But what about port connections? I know ...
- 652
0
votes
0
answers
139
views
Explanation for VHDL loops not going to completion
I am making a mockup CPU in VHDL. I am using Vivado for simulation and programming environment. I need help understanding why my simulation won't follow through with the nestled loops.
I need ...
2
votes
1
answer
114
views
Is it okay to use level-triggered registers on an FPGA? [closed]
I'm trying to make a single-cycle processor and I was planning on doing something like the following:
Clock rising edge: Opcode is latched onto output of block memory (this must be on a rising edge), ...
0
votes
0
answers
127
views
Why may a function return arrays of different sizes, but a constant may not be used the same way?
In a previous question, I noted that this is not allowed in VHDL 2008:
type pipi is array (natural range <>) of bit;
type papa is array (natural range <>) of pipi;
constant foo : papa := (...
- 208
-3
votes
1
answer
119
views
Using Finite State Machine model to design LCD1602 driver in VHDL [closed]
I am designing a driver of the classic LCD1602 module by VHDL. There are many good examples on the web. But when I tried to write it in my own way, I just can't make it work. Here is my code.
library ...
- 21
1
vote
0
answers
102
views
Vivado: Differing behavior between Behavioral and Post-Synthesis Functional Simulation
I'm trying to describe a generic multi-bit register, with N bit input and output signals, a reset bit and an enable bit for writing to the register, but even though it works properly in the behavioral ...
- 355
1
vote
1
answer
81
views
VHDL Generic number concatenation of std_logic_vector
I have an array of std_logic_vectors. The length of the array and std_logic_vectors are variable based on generics. How can I concatenate all the std_logic_vectors in my array without knowing the ...
- 113
0
votes
0
answers
141
views
Why is an array whose elements are arrays with non-identical ranges not allowed, even if all indices and values are constants?
Consider these types
type pipi is array (natural range <>) of bit;
type papa is array (natural range <>) of pipi;
This constant declaration is allowed and the index constraint on (each?) ...
- 208
0
votes
1
answer
177
views
Variable length unsigned in VHDL function
I want to create an unsigned in a function whose length is determined by the function parameters. I thought that was a legit thing to do- pretty sure I've even done it before, but maybe not- but ISE ...
- 119
1
vote
1
answer
111
views
Why does my Mealy FSM written in VHDL get stuck in the wrong state at the end?
I'm making a beverage vending machine with the inputs: clk, reset, leu1(1 of currency), lei5(5 of currency), 10lei(10 of currency), 3 product inputs: product_3lei(costs 3 of currency), product_5lei(...
-3
votes
1
answer
110
views
Statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition(vhdl)
There is a code that should switch CHG_UP if the OVR and UND variables are switched.
entity switcher_for_diod is
Port ( OVR : in STD_LOGIC;
UND : in STD_LOGIC;
CHG_UP : out ...
-1
votes
1
answer
136
views
No signals using library ieee_proposed using Newton-Raphson refinement
I use the ieee_proposed library and try to do a newton-raphson refinement. The code compiles and simulates, but I get no signals. It works with float32 in the library ieee.float_pkg.all. But, I want ...
1
vote
1
answer
82
views
How does the signal value change if it's own value is used to calculate it?
I am a am currently studying VHDL and I have encountered an interesting problem.
I have created an entity Sklop with the architecture Beh2:
entity Sklop is
port (
x : in bit;
y : in bit;
...
- 51
-1
votes
1
answer
112
views
How to form a Qualified Expression of an Array Type with a Single Element?
Consider a situation where you need to initialise an (1D) array with a length of one, hence containing a single element, using a qualified expression, like this1:
-- Declaration of type of an integer ...
- 35.3k
0
votes
1
answer
99
views
Constant expression required width mismatch in assignment. Non synthesizable VHDL code line
I'm trying to implement a floating point adder/subtractor. I've already achieved the code to work. When I run the simulation it works as expected.
The thing is when I try to synthesize it in Vivado I ...
- 37
1
vote
1
answer
92
views
Combinational logic warning
The following code results in a combinational logic warning but I don't see it. Perhaps someone here can explain.
process(clk_count_400hz)
begin
if (clk_count_400hz <= x"002710") then
...
- 21
1
vote
1
answer
105
views
VHDL error, unsigned on the LHS and RHS of assignment
Questa gives this error (compiling with -2008 on EDA Playground)
-- Compiling architecture rtl of foo
** Error: design.vhd(31): Type error resolving infix expression "xnor" as type ieee....
- 2,620
-1
votes
1
answer
109
views
How does Verilog handle posedge vs VHDL's rising_edge()?
I have been learning Verilog for a class I am taking and ran across something a bit strange to me. If I were to write a DFF in VHDL (which I am more used to), I would do something like:
DFF : process(...
- 86
1
vote
1
answer
82
views
VHDL Type Conversion Error: cannot convert type "universal_integer" to type "MemoryArray"
When compiling my vhdl code is get a conversion error at line 28.
Error:
Error (10305): VHDL Type Conversion error at registers.vhd(28): cannot convert type " universal_integer" to type &...
1
vote
2
answers
114
views
In VHDL, assigning a 2D array of std_logic using initialization array of integers... (slv_2dim, sls_2dim, slu_2dim)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity design1 is
end entity;
architecture beh of design1 is
type slu_2dim is array (natural range <>, natural range &...
- 6,771
-2
votes
1
answer
122
views
VHDL signal not assigned in every case statement [closed]
If I have a the following case statement in a VHDL code
case state is
when ST_STATE1 =>
a <= '1';
when ST_STATE2 =>
b <= '1';
when ST_STATE3 =>
a &...
- 1,154
-1
votes
1
answer
78
views
Executing intermediate signals in 1 clock cycle inside a clocked process in VHDL
Let's say I have a signal B that evaluates its value from signal A. It's messy to write the whole operation in one line so I would like to use an intermediate signal A_rounded (my actual code is a lot ...
- 11
-4
votes
1
answer
193
views
High Level Synthesis Stream splitting inside a function (FPGA openCV acceleration)
i try to split a HLS stream which is incoming from the interface. This stream contains a data stream and a user stream with control signals (startFrame, stopFrame, startLine, etc).
I want to use an xf:...
- 1
0
votes
1
answer
130
views
16-bit ALU with multiplication - splitting 32-bit product for 16-bit output?
I'm having a hard time realising the multiplication process inside my 16-bit ALU. The obvious problem is that I have 2 16-bit inputs and one 16-bit output when the result is actually of 32-bits. I ...
1
vote
1
answer
145
views
Error when trying to read binary file in VHDL
I am trying to write a VHDL simulation module that reads a binary file containing 16-bit input samples. The code is as follows :
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
...
-2
votes
1
answer
122
views
Correct alias syntax in GHDL
I'm implementing my first RISC-V processor in VHDL-2008. For simulation I'm using GHDL (version 5.0). The processor structure looks like this:
my_implementation
|
|___test.vhd - ...
- 1
-2
votes
1
answer
154
views
Mismatch between behavioral simulation and post-synthesis functional simulation in vivado
I am writing a VHDL module to convert an incoming stream via axi stream (tdata, tvalid, tready and tlast) with tdata's with 8 bits such that the fist 4 bytes are registered in the output port A of 32 ...
- 57
0
votes
2
answers
201
views
Vivado VHDL: attribute 'stable not implemented
I am trying to detect when an oscillating signal stops oscillating. I thought the best approach would be to use the 'stable attribute. When I go to synthesis, it gives an error saying "attribute '...
- 25
0
votes
2
answers
88
views
What is the utility of a "clock'event" if the sensitivity list has a single signal and is tested at 1?
I was wondering what is the difference between
process (clk)
if (clk = '1') then
and
process (clk)
if (clk'event and clk = '1') then
I thought the sensitivity list defined on which signals a state ...
- 11
-1
votes
1
answer
173
views
Verilog slice direction differs from VHDL
I have a VHDL entity with some unconstrained std_logic_vector ports that is wrapped by a verilog module that clearly defines those port widths.
Verilog wrapper:
module conv_wrapper (din,dout,clk,ce);
...
- 31
-1
votes
1
answer
796
views
how to force block ram instead of LUT in VHDL?
xc7s25csga225-1 FPGA
Vivado v2023.2.2 (64-bit)
VHDL
i keep getting the error:
[DRC UTLZ-1] Resource utilization: F7 Muxes over-utilized in Top Level Design (This design requires more F7 Muxes cells ...
0
votes
1
answer
102
views
Is there a way to use a subtype definition to constrain an array element?
Say I have the following type definitions:
type my_type is record
a : std_logic_vector;
end record;
type my_type_a is array (integer range <>) of my_type;
subtype my_subtype is my_type(a(7 ...
- 9