832 questions
0
votes
0
answers
54
views
Verilog & Vivado - How to load memory initialization files into BRAM on post-synthesis simulations
I am designing a 16 bit microcontroller for a college project using Vivado and Verilog. On behavioral simulations i use $readmemh and everything runs fine, the instructions are loaded from memory and ...
2
votes
2
answers
82
views
Proper way of resetting a FSM
I usually work with Xilinx FPGA boards. Based on the documentation I've reviewed and the research I've done, I try to avoid using a global reset signal in my designs as much as possible. However, let'...
- 21
-1
votes
1
answer
89
views
`$display` output wrong result when caculate `-3*3`?
module te(
input a
);
reg clk;
reg [1:0]d1=2'd3;
reg signed [2:0]d2=-3'd3;
reg signed [4:0]d3;
always @(posedge clk) begin
d3<=d1*d2;
$display("%b",d3);//01111,how to know the ...
- 2,513
0
votes
0
answers
44
views
`ERROR: [VRFC 10-4982]` and `ERROR: [VRFC 10-8885]` through instantiation [duplicate]
`timescale 1ns/1ps
module ctrl(
output d0,
output reg d1,
output reg res=1'b1,
output reg d3,
output reg d4
);
reg [7:0] oper_cnt=8'd0;
reg clk;
assign d0=clk;
always @(...
- 2,513
-3
votes
1
answer
166
views
`ERROR: [VRFC 10-2063] Module <my_task> not found while processing module instance <'Undefined'>` when using verilog task [closed]
`timescale 1ns/1ps
module m_top
(
input GCLK,
input [7:0] i_in1,
output o_out1,
output reg o_out2,
inout io_data,
output reg[7:0]yy
);
assign o_out1=5;
initial o_out2=6;
task my_task;
input a,b;
...
- 2,513
0
votes
1
answer
80
views
How to print array value in VerilogHDL?
`timescale 1ns/1ps
module m_top
(
input GCLK,//100MHz,Y9
input [7:0] i_in1,
output o_out1,
output reg o_out2,
inout io_data
);
reg hh [2:0][1:0] ;
reg [2:0]hh2[1:0] ;
always @(negedge GCLK)begin
...
- 2,513
-1
votes
1
answer
73
views
How to print the correct value of a signed reg variable?
`timescale 1ns/1ps
module a(
input a,
output [7:0]tmp
);
reg signed[2:0] m;
reg [2:0] n;
initial begin
m=4;
n=4;
$display("%f",m);//-4.000000
$display("%f",n);//4.000000
end
...
- 2,513
-4
votes
1
answer
203
views
Why is `-3'd300>5000` true in Verilog? [duplicate]
`timescale 1ns / 1ps
module m_top
(
input GCLK,//100MHz,Y9
output reg o_out2,
inout io_data
);
initial begin
if(-3'd300>5000)begin
$display("%b",-3'd300);//...
- 2,513
-6
votes
1
answer
97
views
`ERROR: [VRFC 10-2951] 'xxxx' is not a constant` when use verilog case function
`timescale 1ns / 1ps
module m_top
(
input GCLK,
output o_out2,
inout io_data
);
reg [2:0] compare;
case(compare)
3'd1:begin
assign o_out2=1;
end
3'd2:begin
assign o_out2=2;
end
default:begin
...
- 2,513
2
votes
2
answers
169
views
In Vivado, what is "[Synth 8-7213] Expression condition using operand 'x' does not match with the corresponding edges used in event control" error?
When I am doing some development with Verilog and Vivado, I wrote some Verilog code as follows:
module min_rep_example_A(input clk, input rst_n, output reg[3:0] LED);
always @(posedge clk or ...
- 78
0
votes
0
answers
98
views
Vivado Block Memory Generator IP not accepting COE file
Here is my python script to generate a COE file:
import numpy as np
def generate_coe_file(filename, data_list, radix=16):
with open(filename, 'w') as f:
f.write(f"...
0
votes
0
answers
71
views
Why does module instantiation affect output reg value in vivado? [duplicate]
The instantiation module as below:
module second_module(
input [7:0] d,
output reg [7:0] q
);
initial
q <= ~d;
endmodule
The top module as below:
module top_module(
input [7:0] ...
- 2,513
0
votes
1
answer
88
views
`$strobe` and `$display` output different result for the same target
Refer to this question,I write a similar case.
module n;
reg [1:0]a, b;
initial begin
a=1;
a<=a+1;
$strobe("strobe",a);
$display("display",a);
end
endmodule
The ...
- 2,513
0
votes
1
answer
61
views
`$display` cannot display right value in vivado
`timescale 1ns / 1ps
module factorial(
input i_n,
output reg res,
input i_clk
);
integer j;
initial
begin:a
for (j=1;j<=i_n;j=j+1)begin
res<=res*j;
end
res<='d3;
$display("res is ...
- 2,513
-1
votes
1
answer
251
views
How to set up handler for microblaze interrupt?
I'm trying to use microblaze interrupt to handle with simple gpio button interrupt. In the block, only gpio and uart is used as well as interrupt controller. Interrupt controller is set for level ...
- 11
2
votes
2
answers
221
views
Efficient 16-bit std_logic_vector comparator in VHDL
I'm working on a VHDL project where I need to implement a comparator between two 16-bit std_logic_vector signals, a and b. The goal is to check if a is greater than, less than, or equal to b.
The ...
- 21
0
votes
1
answer
78
views
Large amounts of data cannot be transferred to the address of the bram controller
I want to send 65536 data to address of block memory(bram) controller MoveDataDMA(source6, destination6, 65536);, but it gets stuck in while ((Done==0) & (Error==0));. when I try to MoveDataDMA(...
- 27
-1
votes
1
answer
131
views
`get_ports *` cannot find port,deliver `WARNING: [Vivado 12-584]`
Sample verilog script as below:
`timescale 1ns/1ps
module Save_Mult_Df(Abar,Bbar,Cbar);
input Abar;
output Bbar;//Bbar is here
input Cbar;
assign Bbar=Abar+Cbar;
endmodule
module test();
reg Abar,...
- 2,513
-1
votes
1
answer
177
views
How to use `get_nets` to find `wire` in Vivado when get Vivado 12-1023 warning?
Verilog script as below:
`timescale 1ns/1ps
module Save_Mult_Df(A);
input A;
wire C;
assign C=A;
endmodule
module test();
reg A;
wire C;//should wire be added to testbench?
initial
A= 2'b10;
...
- 2,513
1
vote
1
answer
82
views
No expected result when using Vivado. What's the problem with the testbench file?
I tried to reproduce loadable counter in Vivado 2023.1, but I cannot get expected result.
My testbench file is below:
`timescale 1ns / 1ps
module behav_counter();
reg [7:0] d;
reg clk;
reg ...
- 2,513
1
vote
1
answer
214
views
Vivado bi-directional INOUT signal on non-top-module
I've recently started working with bi-directional data transfer.
I wrote a simple Verilog module that takes an input in one clock cycle and returns a processed result (by adding one) after the bus ...
- 758
0
votes
0
answers
139
views
Explanation for VHDL loops not going to completion
I am making a mockup CPU in VHDL. I am using Vivado for simulation and programming environment. I need help understanding why my simulation won't follow through with the nestled loops.
I need ...
1
vote
1
answer
329
views
Why is my waveform not showing on Vivado?
module DCP_21(
input a,
input b,
output w,
output x,
output y,
output z
);
assign w = ~(a & b);
assign x = ~(a | b);
assign y = a^b;
assign z = ~(...
- 11
0
votes
0
answers
53
views
Why HLS C++ code generates non specified input?
I'm learning the basics of High-Level Synthesis (HLS) using AMD/Xilinx tools. Most courses use older tools for the practical examples (Vivado HLS instead of Vitis 2024.2 which I'm using).
This is the ...
0
votes
1
answer
346
views
What's the difference between a constant and an inline constant in Vivado?
I'm currently working on a simple project on an FPGA and wanted to set an enable-input to 1. Now when using the built in IPs for a constant, two components show up. One is "Constant" and the ...
- 13
1
vote
1
answer
70
views
Xilinx 7 overwrite LUT contents after flashing
I want to be able to change device behavior during work
Can I overwrite INIT values of LUT within FPGA work process?
I've seen, that I can use it as LUTRAM, but I also want to be able to shift data ...
- 181
1
vote
0
answers
102
views
Vivado: Differing behavior between Behavioral and Post-Synthesis Functional Simulation
I'm trying to describe a generic multi-bit register, with N bit input and output signals, a reset bit and an enable bit for writing to the register, but even though it works properly in the behavioral ...
- 355
0
votes
1
answer
257
views
TCL Script for Including Date and Time in Top Module of Design Sources in Vivado
I’m trying to write a TCL script in Vivado 2021.2 that dynamically includes the current date and time in my top module by fetching the name and path of the top module.
The following TCL command works ...
- 11
1
vote
1
answer
111
views
Why does my Mealy FSM written in VHDL get stuck in the wrong state at the end?
I'm making a beverage vending machine with the inputs: clk, reset, leu1(1 of currency), lei5(5 of currency), 10lei(10 of currency), 3 product inputs: product_3lei(costs 3 of currency), product_5lei(...
1
vote
1
answer
134
views
LED Sequence on Basys3 with Verilog
I need this for a school project. The professor wants an LED sequence if the x is zero (which would mean the sw is 0) that would go:
0000000000000001
0000000000000010
0000000000000100
0000000000001000
...
- 51
-1
votes
1
answer
136
views
No signals using library ieee_proposed using Newton-Raphson refinement
I use the ieee_proposed library and try to do a newton-raphson refinement. The code compiles and simulates, but I get no signals. It works with float32 in the library ieee.float_pkg.all. But, I want ...
1
vote
1
answer
97
views
Vivado behavioral simulation results differ on different PCs, but synthesis results are the same
I have implemented a BCD converter on which I worked from two different PCs:
A computer (AMD Ryzen 7 3700X 8-Core processor, GeForce RTX 2070 SUPER, 32GB ram - Windows 10)
A laptop (Intel i7-1165G7 ...
- 35
1
vote
1
answer
66
views
Output is X when 1, but correct as zero
I'm trying to play "Happy Birthday" using the Basys3.
For some reason the simulation value of the output is X instead of 1:
The outputs are:
clk_440
sound
sound_tb
Each of a different ...
0
votes
1
answer
113
views
Vivado 2018.3 generate bitstream consume a lot of time
I am using Vivado 2018.3(on Ubuntu 22.04) and my project is about pcie xdma,not very big project.
The syn and implementation part takes about 5 minutes , and it report time failed.
But I want to ...
- 21
0
votes
1
answer
92
views
Vitis HLS change of datatype makes variable unused
I'm trying to implement a signal processing algorithm in Vitis HLS.
For this, I read in a few variables via AXI Stream and AXI Lite.
Simulation and synthesis did already work with the complete project....
- 41
2
votes
1
answer
1k
views
Vivado design checkpoint
I am quite new to this.
Hopping into an existing project, which had both bin and dcp files commited in to git. These have constant conflicts, which makes sense to me. As generated files, my take is ...
- 42.4k
0
votes
1
answer
2k
views
How to use vivado on the command line (compile and simulate only)
I find the Vivado IDE to be very unwieldy, particularly for small classroom demos.
I would like to just use a text editor, the compiler, and the graph displayer.
In icarus verilog, it's easy:
iverilog ...
- 8,644
0
votes
1
answer
49
views
Problems opening FOC motor control app in Vivado 2023.2
I have bought the Kria KD240 Starter Kit to get used to working with drives applications and FOC control. I am following the steps mentioned here but I can't open the Vivado project correctly. When I ...
- 1
1
vote
1
answer
79
views
Xilinx Vivado 2023 IP block design issue: Unable to connect output of RTL module to AXI GPIO output that is connected to LED
I am using Vivado 2023.1, and I am not able to connect the output of the RTL module to the AXI GPIO output that is connected to the LED. Please take a look at the attachment. RTL is below
module ...
- 469
-2
votes
1
answer
154
views
Mismatch between behavioral simulation and post-synthesis functional simulation in vivado
I am writing a VHDL module to convert an incoming stream via axi stream (tdata, tvalid, tready and tlast) with tdata's with 8 bits such that the fist 4 bytes are registered in the output port A of 32 ...
- 57
0
votes
2
answers
201
views
Vivado VHDL: attribute 'stable not implemented
I am trying to detect when an oscillating signal stops oscillating. I thought the best approach would be to use the 'stable attribute. When I go to synthesis, it gives an error saying "attribute '...
- 25
-1
votes
1
answer
173
views
Verilog slice direction differs from VHDL
I have a VHDL entity with some unconstrained std_logic_vector ports that is wrapped by a verilog module that clearly defines those port widths.
Verilog wrapper:
module conv_wrapper (din,dout,clk,ce);
...
- 31
0
votes
1
answer
164
views
Define custom attributes for a record
Say I have a custom record type:
type CustomRecord is record
S : signed;
V : std_logic;
end record;
We instantiate this by using
signal X : CustomRecord(S(21 downto 0))
which is fine. But ...
- 1
-1
votes
1
answer
347
views
D-type Flip Flop - Behavioral vs Gate-Level Modeling in Verilog, Timing of state transitions
Modeling a D-type Flip Flop in Verilog with gate-level modeling vs. behavioral modeling seems to result in state transitions happening at different edges of the clock signal. I'm sure I'm missing ...
- 1
0
votes
1
answer
78
views
How should task be used?
I decided to use verilog task feature to write generic and readable code and I'm having trouble with it.
When I write and call it with Task, it does not see the outputs of the circuit, it only writes ...
- 1
0
votes
1
answer
156
views
How do I get the directories of the IP-cores of the Vivado project?
There is a get_ips function, it returns a list of names of all IP-cores of the project. Is there any way to get the directories where the files of these IP-cores are located by some function?
-2
votes
1
answer
424
views
How to handle the read latency in Async FIFO?
I am using Xilinx FIFO generator core in my project. I have module, say M1, which assersts fifo_rd_en signal to the fifo that i am using. However, the fifo has a read latency of 2 clock cycles. How ...
0
votes
1
answer
1k
views
How to simulate Xilinx IP-cores in Modelsim?
I have Vivado 2016.4 and Modelsim 2021.3 installed. My Vivado project contains Xilinx ip-cores. I want to model everything in Modelsim. It is useless to choose the Modelsim simulator in the simulation ...
1
vote
1
answer
123
views
Is CRC Calculation Faster on Xilinx Alveo U280 FPGA Using a Custom Algorithm or a Lookup Table?
I am working on a project where I need to implement CRC (Cyclic Redundancy Check) on a Xilinx Alveo U280 FPGA. I am considering two approaches for CRC calculation and would like to understand which ...
- 256
0
votes
1
answer
239
views
Timing simulation in Vivado giving an error
I am trying to implement and simulate ring oscillators in Xilinx Vivado with the LUT6 primitive. When running the Behavioral Simulation it runs fine, and I can see the signal switch every 5 ns due to ...
- 13