143 questions
0
votes
0
answers
89
views
What is the .tcl command for Cadence Genus to disable scan chain while synthesizing the RTL Design
When I'm placing a Standard I/O Cell in Cadence Innovus, Tool is throwing an error as your design contains scan chains, so I want to disable the scan chain while performing synthesis of Design in ...
0
votes
0
answers
132
views
How to bypass +notimingcheck and +nospecify in vcs with DJ flow
My intention is to annotate sdf file with gate netlist. But due +notimingcheck and +nospecify switches enabled by default from the tool getting notices like below in run.log
Notice: timing checks ...
0
votes
0
answers
42
views
2 Stage Synchronizer confusion
In this picture, Ds goes metastable during the second rising edge of CLK-B because Din changed values during its aperture time at the first rising edge of CLK-B. However, Ds can go metastable during ...
-1
votes
2
answers
111
views
Bidirectional simulation of nmos/pmos in Verilog
I am trying automatically generate Verilog from VLSI stick diagrams for logical output validation. The problem I am running into is that in general, transistors in VLSI are symmetrical, but the ...
- 195
0
votes
1
answer
201
views
Synopsys VCS- System verilog compilation option for smart ordering of files
I have two files in SystemVerilog. One file is importing the package defined in a different file as follows:
import singlePort_Scalar_DUT_pkg::* ;
I am trying to analyze these files using following ...
1
vote
1
answer
134
views
It's supposed to be a MOD10 counter but it counts from 0 to 9 and resets to 4. Why?
It's supposed to be a MOD10 counter, but it counts from 0 to 9 and resets to 4. Why? Please give me the solution as a code and explanation for it if possible.
module MOD10 (clk, clr, q);
input ...
- 11
1
vote
1
answer
82
views
ERROR VCP2000 "Syntax error. Unexpected token: initial." "testbench.sv" 50 7
I am not able to find the exact reason for the error here. Can anyone help me?
`include "uvm_macros.svh"
import uvm_pkg::*;
class my_driver extends uvm_driver;
`uvm_component_utils(...
0
votes
1
answer
261
views
How can I execute a primetime command through a perl script
I am converting a TCL script to perl.
I have tried it using the system command and back tics. I am executing the perl script in primetime in the following way,
exec script.pl.
The script contains many ...
- 1
-1
votes
1
answer
84
views
Not getting the full Timing Report in Synthesis Report
I wrote a code for Register Bank and synthesized on ISE software but I am not getting the Full Timing Report , specifically delay of the design (Section under Synthesis Report). Maybe it is because of ...
- 1
-1
votes
1
answer
101
views
Reducing OR not working as expected when bit slicing in a loop
As for the title reducing OR not working as expected when bit slicing in a loop.
This is an extract of what I have:
logic [3:0][1:0] quad_mask_dq_qq;
logic [1:0] dfifo_rrdy_qq;
always_comb ...
- 23
1
vote
1
answer
277
views
UVM testbench for APB driver run_phase logic
In the driver_class run_phase code below, I am not able to understand how to write the logic to send the transaction to the DUT.
Can we give Penable, Psel, Pready values manually in the driver class ...
- 19
-1
votes
1
answer
81
views
Testbench for writing to the file in Verilog
This is my Testbench for a design and I am applying inputs to the design using the function '$readmemb'.
I have opened a file using '$fopen' and wish to write the result 'out' in the file named 'jaja....
- 1
0
votes
2
answers
327
views
SystemVerilog unconnected port
I am wondering if there is any difference between these two connections, I know the first case can accept default value, but my question is rather from a netlist point of view :
Unconnected port
...
- 35
-1
votes
1
answer
207
views
Getting this: Null object access
Am getting this Error the below error, as of my knowledge as per this error message am going to access an empty object.
Error-[NOA] Null object access
generator.sv, 23
The object at dereference ...
- 19
1
vote
2
answers
474
views
Is it possible to write task/function inside an interface?
Inside the interface, usually we declare clocking blocks and modports. Is it possible to declare any task or function inside the interface?
If yes, tell me any example scenario.
- 19
1
vote
1
answer
55
views
Getting Incorrect output for Layered Testbench for a Full Adder
I have designed a Full-Adder just to get hands-on Layered Testbench Methodology for a Full-Adder with the Design, Interface, Transaction Class, Generator Class, Driver Class, Monitor Class, Scoreboard ...
- 11
0
votes
1
answer
175
views
Are FPGA GPIOs capable enough to read bits at a high rate (26Mbps)? If not, what is a possible way? [closed]
I had two systems, let's say, system A and system B, so system A generates bits at the rate of 26Mbps from a physical pin, I need to capture/read all the data with system B which is ZC706 FPGA/any ...
1
vote
1
answer
77
views
Shift and add binary multiplier getting don't-cares for reg2
module bin_mult(
output reg [7:0]mult,reg1,reg2,
output reg [2:0]count,
input [3:0]a,b,
input load,clk);
//reg [7:0]reg1,reg2;
//reg [2:0]count;
reg [3:0]m[3:0];
...
- 31
0
votes
1
answer
128
views
NgSpice Installation
I'm encountering an error while trying to compile ngspice, and I'm seeking assistance in resolving it. When compiling the bsimbulk module, I'm encountering the following error:
In file included from ...
0
votes
1
answer
201
views
Why Ac_cdc01d rule in synopsis spyglass CDC is disabled by default?
I tried enabling this rule and ran spyglass, (I have 2 clocks of same frequency and phase).
Still I'm getting a errors in cdc_verify saying data hold check failed in fast to slow clock transfer even ...
0
votes
1
answer
75
views
Error in the code I am unable to solve it and i am unable to prevent the error
I am getting mixed port connection problem
can anybody help me
I was trying to instantiate the previous module into the new module
.data_out(level1_1_out),
.data_in(data_in1),
.Cx(Cx1),
.clk(clk)
...
-2
votes
1
answer
114
views
Regarding "D0" drive strength cell
Why in the design we do not use or consider "D0" & "D20" drive strength cell in design?
is there are any reason related to the chip aging? if yes please explain me
or if you ...
0
votes
1
answer
215
views
STA of 2 clocks with the same frequency
Imagine a design has 2 input clocks. They have the "same" nominal frequency but originate from 2 different sources and therefore are asynchronous to each other.
The clocks are defined as ...
- 179
0
votes
1
answer
2k
views
what does Innovus dbGet command top.insts.cell.baseClass mean ? what are these values of top.insts.cell.baseClass mean?
dbGet command can be used to retrieve all the instances of the top block but exactly what are these values insts.cell.cellbaseClass?
how can I change them to point certain other level of hierarchy ...
- 129
0
votes
1
answer
138
views
"assign" followed by "always" - what is the order of evaluation?
I found the following MAC code in a verilog course and I am not able to make sense of how the MAC unit's earlier output is being fedback to the adder so that it can add this to the multiplier output.
...
- 479
0
votes
1
answer
452
views
Does adding buffer in a digital path increase the delay or reduce the delay and why?
I am confused as I have seen that in some cases it increases the delay and in some cases it reduces the delay
user19457634
2
votes
1
answer
6k
views
how to declare integer variable in verilog to keep track of a value to be used in multiple for loops?
so I have this assignment to make a generic Wallace tree multiplier in Verilog, I wrote the code but didn't test it yet. my problem is in the 2nd stage where I am supposed to bypass some wires which ...
- 1,913
0
votes
2
answers
1k
views
Verilog [dot] meaning?
What does this " .depth_log2(7) " and .i_wclk mean in Verilog code?
asynch_fifo #(.depth_log2(7),
.data_width(22),
.rd_flop1_megedge(1'b1),
) USB2_ASYNCH_FIFO (
.i_wclk(...
2
votes
1
answer
7k
views
What is the difference between 2'b0 and 2'd0?
I was tying a port to zero in my design. What is the difference between 2'b0 and 2'd0 in Verilog?
What does b and d actually mean?
- 21
0
votes
1
answer
970
views
What's the difference between `transaction and `transaction`event in VHDL
I understand that event is when the signal *transitions* to/from a value. transaction is when a signal is assigned a value, even if the value is the same as the previous value.
My question is what is ...
- 11
-1
votes
2
answers
1k
views
Scoreboard in UVM
What do we do when we have to create a scoreboard for a certain design logic? For a memory I understand that we can compare the data written to DUT at a certain address to the data read at the same ...
- 13
0
votes
1
answer
1k
views
What is the Difference Between Actual and Formal Arguments in Systemverilog DPI?
In SystemVerilog design I am using DPI-C with c program functions. While running simulation on both files, I am getting error:
"Actual type is not supported for DPI open array".
I want to ...
- 47
0
votes
1
answer
925
views
How can I reset my SoC from cmm script using RISC-V trace32 debugger. I don't have TRST or SRST serial lines connected to SoC
My cmm script is something like this :
..start of cmm script
""GTL config and GTL connect""
""some JTAG.SHIFT operations""
JTAG.PIN DISable
system.mode prepare ...
- 1
2
votes
1
answer
7k
views
Is there an open source H.264 implementation on FPGA?
I want to design and implement an H.264 baseline/main profile encoder on FPGA for real-time HD video processing. To begin with, I am looking for design examples that would help me to understand the H....
- 41
1
vote
1
answer
970
views
Verilog basic gate data flow not working for NAND & NOR, but works for XNOR & XOR
I have some basic code using data flow statements, but nor and nand functions are not working with this.
module basic_gates_bitwise_df(
input A,
input B,
output andd,orr,nota,nandd,norr,xorr,xnorr
);
...
- 23
0
votes
2
answers
924
views
Difference between shift operation using concatenate operator {} and shift operator << in verilog
reg [3:0]a;
reg in;
a <= {a[2:0],in}; //1- Using Concatenate
Operator
a <= a<<1; //2- Using Shift operator
What is the difference between 1 & 2 in terms of:
...
- 11
0
votes
1
answer
198
views
applying stimulus to FPGA using PC
Is there any way I can apply stimulus signals on my FPGA board from my PC itself, and view the output of hardware in any simulation software? I am working on Spartan 3A development board provided by ...
- 11
3
votes
2
answers
823
views
Error: (vlog-2110) Illegal reference to net "code"
I have tried this code, but it shows the error:
gray_counter\gray_counter.v(2): (vlog-2110) Illegal reference to net
"code"
module gray_counter(code,clk,rst,count);//module declaration
...
- 31
0
votes
1
answer
60
views
Scaling delay values in Design compiler topographical
I want to scale delay values in TLU plus file to zero . How can we achieve that in design compiler topographical mode. How can we scale delay values to zero of TLU plus file in DC topo
-1
votes
2
answers
349
views
XOR of variables in consecutive clock cycle
I am just learning to code in verilog. I want to XOR three variable in consecutive clock cycles. For example Z1 from 1st clock cycle ,Z2 from 2nd clock cycle and Z3 from 3rd clock cycle. How can I do ...
- 17
0
votes
1
answer
1k
views
Shift Register in verilog
I have designed a serial in parallel out shift register as input register for an encoder
module ShiftRegister_SIPO(clk, in, out);
input clk,in;
output [3:0] out;
reg [3:0] tmp;
always @(posedge clk)
...
- 17
2
votes
1
answer
3k
views
Systemverilog function synthesis - automatic vs static
In the context of combinatorial logic synthesis (not simulation):
When should a function be declared as automatic ?
When should a function be declared as static ?
- 179
-2
votes
1
answer
2k
views
ERROR :near "initial": syntax error, unexpected initial [duplicate]
This is my code, and I get this compile error:
ERROR :near "initial": syntax error, unexpected initial
How do I fix this error?
module pract_wildcardequality();
logic [3:0] a,b;
function ...
-2
votes
3
answers
4k
views
What is the difference between begin end and fork join with respect to non-blocking statements?
We know that the difference between blocking statements and non-blocking statements is: blocking statements executes sequentially (execution of next statement is blocked until present one completes) ...
1
vote
1
answer
279
views
SRAM simulation in pspice
This is my code for SRAM simulation in pspice
SRAM simulation
VDD 3 0 DC 5V
VWL 4 0 PWL (9us 0V 10us 5V 90us 5V 91us 0V)
VBL1 5 0 PWL (0 0V 1us 5V 100us 5V 101us 0V)
VBL2 6 0 PWL (0 0)
M1 1 2 3 3 PMOS
...
- 11
0
votes
3
answers
532
views
Does SystemVerilog Generate support delays?
I thought of generating clock using genvar like below:
reg [7:0]clk;
genvar i;
generate
for (i=0; i < 7; i++) begin
#1 clk[i]=~clk[i];
...
- 11
-1
votes
1
answer
58
views
How are current generation clock frequencies achieved?
I was recently reading through the design of PLLs and was thinking about how these reference clocks are generated.
We know that the reference is generated from a crystal (Generally Quartz), but the ...
0
votes
1
answer
204
views
Why the vivado 2017.4 is showing error here?
My code is:
module circuilar_fifo;
localparam B=3,W=2;
input wire clk,reset,wr,rd;
input wire [B-1:0] wr_data;
output wire [B-1:0] rd_data;
output wire full,empty;
Isn't this one of the correct ...
1
vote
1
answer
1k
views
What is the diffrence between Non-Consecutive GoTo Repetition Operator and Repetition Non-Consecutive in system verilog?
I'm currently reading Ashok Mehta's system Verilog assertion textbook. Now I have encountered a doubt. I couldn't understand what is the difference between -> and = operator. I.e, Non-Consecutive ...
1
vote
1
answer
3k
views
How to understand the blocking and non blocking statements in verilog?
I understood the basic difference between blocking and non-blocking statements in Verilog. But still it is not possible for me to understand what's happening & when and where to use blocking and ...