| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [NFC][TTI] Add Alignment for isLegalMasked[Gather/Scatter] | Anna Welker | 2019-12-18 | 1 | -4/+6 |
| * | Rename TTI::getIntImmCost for instructions and intrinsics | Reid Kleckner | 2019-12-11 | 1 | -6/+6 |
| * | [ARM] Teach the Arm cost model that a Shift can be folded into other instruct... | David Green | 2019-12-09 | 1 | -6/+6 |
| * | Sink all InitializePasses.h includes | Reid Kleckner | 2019-11-13 | 1 | -3/+4 |
| * | [TTI][LV] preferPredicateOverEpilogue | Sjoerd Meijer | 2019-11-06 | 1 | -0/+6 |
| * | [PGO][PGSO] TargetLowering/TargetTransformationInfo/SwitchLoweringUtils part. | Hiroshi Yamauchi | 2019-10-31 | 1 | -3/+4 |
| * | [Alignment][NFC] getMemoryOpCost uses MaybeAlign | Guillaume Chatelet | 2019-10-25 | 1 | -5/+5 |
| * | [NFC][TTI] Add Alignment for isLegalMasked[Load/Store] | Sam Parker | 2019-10-14 | 1 | -4/+6 |
| * | recommit: [LoopVectorize][PowerPC] Estimate int and float register pressure s... | Zi Xuan Wu | 2019-10-12 | 1 | -2/+10 |
| * | [System Model] [TTI] Move default cache/prefetch implementations | David Greene | 2019-10-10 | 1 | -28/+0 |
| * | [System Model] [TTI] Update cache and prefetch TTI interfaces | David Greene | 2019-10-09 | 1 | -0/+28 |
| * | Revert "[LoopVectorize][PowerPC] Estimate int and float register pressure sep... | Jinsong Ji | 2019-10-08 | 1 | -10/+2 |
| * | [LoopVectorize][PowerPC] Estimate int and float register pressure separately ... | Zi Xuan Wu | 2019-10-08 | 1 | -2/+10 |
| * | Revert "[SLP] avoid reduction transform on patterns that the backend can load... | Martin Storsjo | 2019-10-07 | 1 | -53/+0 |
| * | [SLP] avoid reduction transform on patterns that the backend can load-combine | Sanjay Patel | 2019-10-05 | 1 | -0/+53 |
| * | [NFC][HardwareLoops] Update some iterators | Sam Parker | 2019-10-01 | 1 | -11/+6 |
| * | [Alignment][NFC] Remove unneeded llvm:: scoping on Align types | Guillaume Chatelet | 2019-09-27 | 1 | -3/+2 |
| * | [NFC] remove unused functions | Guillaume Chatelet | 2019-09-16 | 1 | -8/+0 |
| * | [LLVM][Alignment] Convert isLegalNTStore/isLegalNTLoad to llvm::Align | Guillaume Chatelet | 2019-09-05 | 1 | -2/+2 |
| * | [CostModel] Model all `extractvalue`s as free. | Roman Lebedev | 2019-08-29 | 1 | -0/+2 |
| * | InferAddressSpaces: Move target intrinsic handling to TTI | Matt Arsenault | 2019-08-14 | 1 | -0/+10 |
| * | [AMDGPU] Tune inlining parameters for AMDGPU target | Daniil Fukalov | 2019-07-17 | 1 | -0/+4 |
| * | Revert "[HardwareLoops] NFC - move hardware loop checking code to isHardwareL... | Jinsong Ji | 2019-07-09 | 1 | -32/+1 |
| * | [HardwareLoops] NFC - move hardware loop checking code to isHardwareLoopProfi... | Chen Zheng | 2019-07-09 | 1 | -1/+32 |
| * | [PowerPC] exclude ICmpZero in LSR if icmp can be replaced in later hardware l... | Chen Zheng | 2019-07-03 | 1 | -0/+7 |
| * | [HardwareLoops] NFC - move loop with irreducible control flow checking logic ... | Chen Zheng | 2019-06-26 | 1 | -7/+11 |
| * | [HardwareLoops] NFC - move loop with irreducible control flow checking logic ... | Chen Zheng | 2019-06-26 | 1 | -1/+9 |
| * | [ExpandMemCmp] Move all options to TargetTransformInfo. | Clement Courbet | 2019-06-25 | 1 | -3/+3 |
| * | [NFC] move some hardware loop checking code to a common place for other using. | Chen Zheng | 2019-06-19 | 1 | -0/+85 |
| * | [GlobalISel][Localizer] Rewrite localizer to run in 2 phases, inter & intra b... | Amara Emerson | 2019-06-17 | 1 | -0/+4 |
| * | [LV] Suppress vectorization in some nontemporal cases | Warren Ristow | 2019-06-17 | 1 | -0/+10 |
| * | [CodeGen] Generic Hardware Loop Support | Sam Parker | 2019-06-07 | 1 | -0/+6 |
| * | [CostModel] Add really basic support for being able to query the cost of the ... | Craig Topper | 2019-05-28 | 1 | -0/+10 |
| * | [ARM] Implement TTI::getMemcpyCost | Sjoerd Meijer | 2019-04-30 | 1 | -0/+6 |
| * | [ScalarizeMaskedMemIntrin] Add support for scalarizing expandload and compres... | Craig Topper | 2019-03-21 | 1 | -0/+8 |
| * | [TTI] Enable analysis of clib functions in getIntrinsicCosts. NFCI. | Sjoerd Meijer | 2019-03-12 | 1 | -6/+9 |
| * | [LSR] Generate cross iteration indexes | Sam Parker | 2019-02-07 | 1 | -0/+4 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | Only promote args when function attributes are compatible | Tom Stellard | 2019-01-16 | 1 | -0/+6 |
| * | [TTI] getOperandInfo - a broadcast shuffle means the result is OK_UniformValue | Simon Pilgrim | 2018-11-14 | 1 | -0/+7 |
| * | [TTI] Make TargetTransformInfo::getOperandInfo static. NFCI. | Simon Pilgrim | 2018-11-13 | 1 | -2/+1 |
| * | [TTI] Flip vector types in getShuffleCost SK_ExtractSubvector call | Simon Pilgrim | 2018-11-09 | 1 | -1/+1 |
| * | [CostModel] Add SK_ExtractSubvector handling to getInstructionThroughput (PR3... | Simon Pilgrim | 2018-11-09 | 1 | -2/+8 |
| * | [LV] Support vectorization of interleave-groups that require an epilog under | Dorit Nuzman | 2018-10-31 | 1 | -3/+6 |
| * | recommit 344472 after fixing build failure on ARM and PPC. | Dorit Nuzman | 2018-10-14 | 1 | -3/+7 |
| * | revert 344472 due to failures. | Dorit Nuzman | 2018-10-14 | 1 | -7/+3 |
| * | [IAI,LV] Add support for vectorizing predicated strided accesses using masked | Dorit Nuzman | 2018-10-14 | 1 | -3/+7 |
| * | [LoopVectorizer] Use TTI.getOperandInfo() | Jonas Paulsson | 2018-10-05 | 1 | -43/+43 |
| * | Remove trailing space | Fangrui Song | 2018-07-30 | 1 | -9/+9 |
| * | [TargetTransformInfo] Add pow2 analysis for scalar constants | Simon Pilgrim | 2018-07-11 | 1 | -0/+6 |
