| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Sink all InitializePasses.h includes | Reid Kleckner | 2019-11-13 | 1 | -0/+1 |
| * | [DebugInfo] LiveDebugValues: correctly discriminate kinds of variable locations | Jeremy Morse | 2019-09-02 | 1 | -3/+5 |
| * | Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM | Daniel Sanders | 2019-08-15 | 1 | -9/+9 |
| * | [MachineCSE][NFC] Use 'profitable' rather than 'beneficial' to name method. | Kai Luo | 2019-08-07 | 1 | -8/+8 |
| * | Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re... | Daniel Sanders | 2019-08-01 | 1 | -13/+11 |
| * | [MachineCSE][MachinePRE] Avoid hoisting code from code regions into hot BBs. | Kai Luo | 2019-07-19 | 1 | -0/+25 |
| * | [MIR] Skip hoisting to basic block which may throw exception or return | Anton Afanasyev | 2019-06-12 | 1 | -0/+2 |
| * | [MIR] Add simple PRE pass to MachineCSE | Anton Afanasyev | 2019-06-09 | 1 | -9/+118 |
| * | Allow target to handle STRICT floating-point nodes | Ulrich Weigand | 2019-06-05 | 1 | -1/+1 |
| * | Revert r361356: "[MIR] Add simple PRE pass to MachineCSE" | David L. Jones | 2019-05-27 | 1 | -113/+9 |
| * | [MIR] Add simple PRE pass to MachineCSE | Anton Afanasyev | 2019-05-22 | 1 | -9/+113 |
| * | Revert "[MIR] Add simple PRE pass to MachineCSE" | Anton Afanasyev | 2019-05-03 | 1 | -117/+9 |
| * | [MIR] Add simple PRE pass to MachineCSE | Anton Afanasyev | 2019-05-03 | 1 | -9/+117 |
| * | [Codegen] Remove dead flags on Physical Defs in machine cse | David Green | 2019-02-20 | 1 | -19/+24 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again) | Roman Tereshin | 2018-10-20 | 1 | -1/+16 |
| * | [DebugInfo][Dexter] Incorrect DBG_VALUE after MCP dead copy instruction removal. | Carlos Alberto Enciso | 2018-10-01 | 1 | -6/+2 |
| * | [DWARF] Missing location debug information with -O2. | Carlos Alberto Enciso | 2018-08-30 | 1 | -0/+8 |
| * | [MIR][MachineCSE] Implementing proper MachineInstr::getNumExplicitDefs() | Roman Tereshin | 2018-06-12 | 1 | -2/+1 |
| * | Rename DEBUG macro to LLVM_DEBUG. | Nicola Zaghen | 2018-05-14 | 1 | -8/+9 |
| * | [DebugInfo] Examine all uses of isDebugValue() for debug instructions. | Shiva Chen | 2018-05-09 | 1 | -2/+2 |
| * | [MachineCSE] Rewrite a loop checking if a block is in a set of blocks without... | Michael Zolotukhin | 2018-05-04 | 1 | -7/+5 |
| * | GlobalISel: Make MachineCSE runnable in the middle of the GlobalISel | Justin Bogner | 2018-01-18 | 1 | -7/+6 |
| * | MachineFunction: Return reference from getFunction(); NFC | Matthias Braun | 2017-12-15 | 1 | -1/+1 |
| * | [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. | Francis Visoiu Mistrih | 2017-12-07 | 1 | -4/+4 |
| * | [CodeGen] Print register names in lowercase in both MIR and debug output | Francis Visoiu Mistrih | 2017-11-28 | 1 | -5/+5 |
| * | [MachineCSE] Add new callback for is caller preserved or constant physregs | Tony Jiang | 2017-11-20 | 1 | -2/+2 |
| * | Fix a bunch more layering of CodeGen headers that are in Target | David Blaikie | 2017-11-17 | 1 | -3/+3 |
| * | Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering | David Blaikie | 2017-11-08 | 1 | -1/+1 |
| * | [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use wa... | Eugene Zelenko | 2017-08-24 | 1 | -11/+36 |
| * | Sort the remaining #include lines in include/... and lib/.... | Chandler Carruth | 2017-06-06 | 1 | -1/+1 |
| * | CodeGen: Rename DEBUG_TYPE to match passnames | Matthias Braun | 2017-05-25 | 1 | -4/+4 |
| * | MachineCSE: Respect interblock physreg liveness | Mikael Holmen | 2017-05-24 | 1 | -2/+2 |
| * | [codegen] Add generic functions to skip debug values. | Florian Hahn | 2016-12-16 | 1 | -2/+1 |
| * | MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC | Matthias Braun | 2016-10-28 | 1 | -1/+1 |
| * | [CodeGen] Rename MachineInstr::isInvariantLoad to isDereferenceableInvariantL... | Justin Lebar | 2016-09-10 | 1 | -1/+1 |
| * | CodeGen: Use MachineInstr& in TargetInstrInfo, NFC | Duncan P. N. Exon Smith | 2016-06-30 | 1 | -4/+3 |
| * | Re-commit optimization bisect support (r267022) without new pass manager supp... | Andrew Kaylor | 2016-04-22 | 1 | -1/+1 |
| * | Revert "Initial implementation of optimization bisect support." | Vedant Kumar | 2016-04-22 | 1 | -1/+1 |
| * | Initial implementation of optimization bisect support. | Andrew Kaylor | 2016-04-21 | 1 | -1/+1 |
| * | [SSP, 2/2] Create llvm.stackguard() intrinsic and lower it to LOAD_STACK_GUARD | Tim Shen | 2016-04-19 | 1 | -0/+6 |
| * | rangify; NFCI | Sanjay Patel | 2016-01-06 | 1 | -24/+14 |
| * | [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible | Chandler Carruth | 2015-09-09 | 1 | -3/+3 |
| * | MachineCSE: Add a target query for the LookAheadLimit heurisitic | Tom Stellard | 2015-05-09 | 1 | -2/+3 |
| * | Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. | Benjamin Kramer | 2015-03-23 | 1 | -0/+1 |
| * | MachineCSE: Clear dead-def flag on CSE. | Matthias Braun | 2015-02-04 | 1 | -2/+9 |
| * | [MachineCSE] Clear kill-flag on registers imp-def'd by the CSE'd instruction. | Ahmed Bougacha | 2014-12-02 | 1 | -0/+31 |
| * | In Machine CSE pass, the source register of a COPY machine instruction can | Jiangning Liu | 2014-08-11 | 1 | -11/+19 |
| * | Have MachineFunction cache a pointer to the subtarget to make lookups | Eric Christopher | 2014-08-05 | 1 | -2/+2 |
| * | Remove the TargetMachine forwards for TargetSubtargetInfo based | Eric Christopher | 2014-08-04 | 1 | -2/+3 |
