| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | moveOperands - assert Src/Dst MachineOperands are non-null. | Simon Pilgrim | 2020-01-11 | 1 | -1/+1 |
| * | [FPEnv] Invert sense of MIFlag::FPExcept flag | Ulrich Weigand | 2020-01-10 | 1 | -2/+2 |
| * | [MIR] Fix cyclic dependency of MIR formatter | Peng Guo | 2020-01-10 | 1 | -6/+3 |
| * | Revert "Revert "[MIR] Target specific MIR formating and parsing"" | Daniel Sanders | 2020-01-08 | 1 | -8/+11 |
| * | Revert "[MIR] Target specific MIR formating and parsing" | Nico Weber | 2020-01-08 | 1 | -11/+8 |
| * | [MIR] Target specific MIR formating and parsing | Peng Guo | 2020-01-08 | 1 | -8/+11 |
| * | Revert "[MIR] Target specific MIR formating and parsing" | Daniel Sanders | 2020-01-08 | 1 | -11/+8 |
| * | [MIR] Target specific MIR formating and parsing | Peng Guo | 2020-01-08 | 1 | -8/+11 |
| * | [CodeGen] Increase the size of a SmallVector | Jay Foad | 2019-11-15 | 1 | -1/+1 |
| * | [MIR] Add MIR parsing for heap alloc site instruction markers | Amy Huang | 2019-11-05 | 1 | -2/+3 |
| * | Fix unused variable warning. NFCI. | Simon Pilgrim | 2019-10-29 | 1 | -1/+1 |
| * | Recommit "Add a heap alloc site marker field to the ExtraInfo in MachineInstrs" | Amy Huang | 2019-10-28 | 1 | -72/+70 |
| * | Revert "Add an instruction marker field to the ExtraInfo in MachineInstrs." | Amy Huang | 2019-10-25 | 1 | -75/+71 |
| * | Add an instruction marker field to the ExtraInfo in MachineInstrs. | Amy Huang | 2019-10-25 | 1 | -71/+75 |
| * | Prune two MachineInstr.h includes, fix up deps | Reid Kleckner | 2019-10-19 | 1 | -3/+7 |
| * | Remove the AliasAnalysis argument in function areMemAccessesTriviallyDisjoint | Changpeng Fang | 2019-09-26 | 1 | -1/+1 |
| * | [DebugInfo] LiveDebugValues: correctly discriminate kinds of variable locations | Jeremy Morse | 2019-09-02 | 1 | -1/+15 |
| * | [llvm] Migrate llvm::make_unique to std::make_unique | Jonas Devlieghere | 2019-08-15 | 1 | -1/+1 |
| * | CodeGen: Migration to using Register | Matt Arsenault | 2019-08-06 | 1 | -29/+29 |
| * | Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re... | Daniel Sanders | 2019-08-01 | 1 | -17/+15 |
| * | Allow target to handle STRICT floating-point nodes | Ulrich Weigand | 2019-06-05 | 1 | -1/+3 |
| * | [X86] Fix several places that weren't passing what they though they were to M... | Craig Topper | 2019-06-02 | 1 | -1/+1 |
| * | [DebugInfoMetadata] Refactor DIExpression::prepend constants (NFC) | Petar Jovanovic | 2019-05-20 | 1 | -1/+1 |
| * | Recommitting r358783 and r358786 "[MS] Emit S_HEAPALLOCSITE debug info" with ... | Amy Huang | 2019-04-24 | 1 | -0/+13 |
| * | [CodeGen] Add "const" to MachineInstr::mayAlias | Bjorn Pettersson | 2019-04-19 | 1 | -2/+2 |
| * | Allow unordered loads to be considered invariant in CodeGen | Philip Reames | 2019-03-19 | 1 | -3/+5 |
| * | Allow code motion (and thus folding) for atomic (but unordered) memory operands | Philip Reames | 2019-03-14 | 1 | -3/+1 |
| * | [NFC] add/modify wrapper function for findRegisterDefOperand(). | Chen Zheng | 2019-02-20 | 1 | -1/+1 |
| * | Be conservative about unordered accesses for the moment | Philip Reames | 2019-02-11 | 1 | -1/+3 |
| * | Move IR flag handling directly into builder calls for cases translated from I... | Michael Berg | 2019-02-06 | 1 | -11/+18 |
| * | [DEBUGINFO] Reposting r352642: Handle restore instructions in LiveDebugValues | Wolfgang Pieb | 2019-02-04 | 1 | -1/+53 |
| * | [CodeGen] Be as conservative about atomic accesses as for volatile | Philip Reames | 2019-02-01 | 1 | -0/+2 |
| * | Reverting r352642 - Handle restore instructions in LiveDebugValues - as it's ... | Wolfgang Pieb | 2019-01-30 | 1 | -53/+1 |
| * | [DEBUGINFO] Handle restore instructions in LiveDebugValues | Wolfgang Pieb | 2019-01-30 | 1 | -1/+53 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [mips] Emit .reloc R_{MICRO}MIPS_JALR along with j(al)r(c) $25 | Vladimir Stefanovic | 2019-01-17 | 1 | -2/+3 |
| * | Fix MachineInstr::findRegisterUseOperandIdx subreg checks | Stanislav Mekhanoshin | 2018-11-12 | 1 | -3/+1 |
| * | [DebugInfo][Dexter] Incorrect DBG_VALUE after MCP dead copy instruction removal. | Carlos Alberto Enciso | 2018-10-01 | 1 | -0/+10 |
| * | [CodeGen] Always print register ties in MI::dump() | Francis Visoiu Mistrih | 2018-09-26 | 1 | -1/+1 |
| * | Copy utilities updated and added for MI flags | Michael Berg | 2018-09-19 | 1 | -0/+36 |
| * | [MachineInstr] In addRegisterKilled and addRegisterDead, don't remove operand... | Craig Topper | 2018-09-13 | 1 | -2/+4 |
| * | add IR flags to MI | Michael Berg | 2018-09-11 | 1 | -0/+6 |
| * | Fix argument type in MachineInstr::hasPropertyInBundle | Sven van Haastregt | 2018-09-06 | 1 | -1/+1 |
| * | [DWARF] Missing location debug information with -O2. | Carlos Alberto Enciso | 2018-08-30 | 1 | -0/+17 |
| * | Consistently use MemoryLocation::UnknownSize to indicate unknown access size | Krzysztof Parzyszek | 2018-08-20 | 1 | -7/+14 |
| * | [x86/MIR] Implement support for pre- and post-instruction symbols, as | Chandler Carruth | 2018-08-16 | 1 | -25/+67 |
| * | [MI] Change the array of `MachineMemOperand` pointers to be | Chandler Carruth | 2018-08-16 | 1 | -55/+161 |
| * | [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug property | Mikael Holmen | 2018-06-21 | 1 | -12/+34 |
| * | [NFC] make MIFlag accessor functions consistant with usage model | Michael Berg | 2018-06-18 | 1 | -1/+1 |
| * | [MIR][MachineCSE] Implementing proper MachineInstr::getNumExplicitDefs() | Roman Tereshin | 2018-06-12 | 1 | -6/+24 |
