| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re... | Daniel Sanders | 2019-08-01 | 1 | -6/+6 |
| * | [Peephole] Allow folding loads into instructions w/multiple uses (such as tes... | Philip Reames | 2019-06-25 | 1 | -0/+7 |
| * | CodeGen: Introduce a class for registers | Matt Arsenault | 2019-06-24 | 1 | -3/+3 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again) | Roman Tereshin | 2018-10-20 | 1 | -33/+22 |
| * | Re-commit: [globalisel] Add a combiner helpers for extending loads and use th... | Daniel Sanders | 2018-10-03 | 1 | -0/+10 |
| * | Remove trailing space | Fangrui Song | 2018-07-30 | 1 | -1/+1 |
| * | [GlobalISel] NFCI, Getting GlobalISel ~5% faster | Roman Tereshin | 2018-05-23 | 1 | -10/+4 |
| * | IWYU for llvm-config.h in llvm, additions. | Nico Weber | 2018-04-30 | 1 | -0/+1 |
| * | Adding optional Name parameter to createVirtualRegister and createGenericVirt... | Puyan Lotfi | 2018-04-03 | 1 | -4/+5 |
| * | [MIR] Adding support for Named Virtual Registers in MIR. | Puyan Lotfi | 2018-03-30 | 1 | -1/+2 |
| * | GlobalISel: Make MachineCSE runnable in the middle of the GlobalISel | Justin Bogner | 2018-01-18 | 1 | -7/+50 |
| * | MachineFunction: Return reference from getFunction(); NFC | Matthias Braun | 2017-12-15 | 1 | -1/+1 |
| * | [CodeGen] Rename functions PrintReg* to printReg* | Francis Visoiu Mistrih | 2017-11-28 | 1 | -4/+4 |
| * | [MachineCSE] Add new callback for is caller preserved or constant physregs | Tony Jiang | 2017-11-20 | 1 | -0/+7 |
| * | Fix a bunch more layering of CodeGen headers that are in Target | David Blaikie | 2017-11-17 | 1 | -2/+2 |
| * | [MachineRegisterInfo] Avoid having dbg.values affect code generation | Mikael Holmen | 2017-11-16 | 1 | -2/+2 |
| * | Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering | David Blaikie | 2017-11-08 | 1 | -1/+1 |
| * | Reverting r315590; it did not include changes for llvm-tblgen, which is causi... | Aaron Ballman | 2017-10-15 | 1 | -1/+1 |
| * | [dump] Remove NDEBUG from test to enable dump methods [NFC] | Don Hinton | 2017-10-12 | 1 | -1/+1 |
| * | LiveIntervalAnalysis: Fix alias regunit reserved definition | Matthias Braun | 2017-09-01 | 1 | -0/+18 |
| * | Sort the remaining #include lines in include/... and lib/.... | Chandler Carruth | 2017-06-06 | 1 | -1/+1 |
| * | [MIR] Support Customed Register Mask and CSRs | Oren Ben Simhon | 2017-03-19 | 1 | -0/+12 |
| * | Fixing typos. | Oren Ben Simhon | 2017-03-16 | 1 | -4/+5 |
| * | [CodeGen] Fix -Wreorder warning. | Benjamin Kramer | 2017-03-14 | 1 | -3/+3 |
| * | Disable Callee Saved Registers | Oren Ben Simhon | 2017-03-14 | 1 | -2/+34 |
| * | [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ot... | Eugene Zelenko | 2017-02-17 | 1 | -7/+20 |
| * | Cleanup dump() functions. | Matthias Braun | 2017-01-28 | 1 | -2/+2 |
| * | GlobalISel: allow CodeGen to fallback on VReg type/class issues. | Tim Northover | 2016-11-08 | 1 | -11/+0 |
| * | MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC | Matthias Braun | 2016-10-28 | 1 | -2/+1 |
| * | Fix warning; NFC | Matthias Braun | 2016-10-11 | 1 | -2/+2 |
| * | MIRParser: generic register operands with types | Matthias Braun | 2016-10-11 | 1 | -1/+2 |
| * | MIRParser: Rewrite register info initialization; mostly NFC | Matthias Braun | 2016-10-11 | 1 | -7/+10 |
| * | [TargetRegisterInfo, AArch64] Add target hook for isConstantPhysReg(). | Geoff Berry | 2016-09-27 | 1 | -1/+5 |
| * | GlobalISel: remove "unsized" LLT | Tim Northover | 2016-09-15 | 1 | -1/+1 |
| * | GlobalISel: disambiguate types when printing MIR | Tim Northover | 2016-09-12 | 1 | -2/+0 |
| * | GlobalISel: move type information to MachineRegisterInfo. | Tim Northover | 2016-09-09 | 1 | -14/+14 |
| * | MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/... | Matthias Braun | 2016-08-24 | 1 | -1/+6 |
| * | [GlobalISel] Introduce an instruction selector. | Ahmed Bougacha | 2016-07-27 | 1 | -0/+14 |
| * | [GlobalISel] Mark newly-created gvregs as having a bank. | Ahmed Bougacha | 2016-07-19 | 1 | -2/+5 |
| * | [IPRA] Properly compute register usage at call sites. | Chad Rosier | 2016-07-11 | 1 | -2/+3 |
| * | Replace MachineRegisterInfo::TracksLiveness with a MachineFunctionProperty | Derek Schuff | 2016-04-11 | 1 | -2/+1 |
| * | [MachineRegisterInfo] Track register bank for virtual registers. | Quentin Colombet | 2016-04-07 | 1 | -1/+6 |
| * | Replace MachineRegisterInfo::isSSA() with a MachineFunctionProperty | Derek Schuff | 2016-04-04 | 1 | -2/+2 |
| * | [MachineRegisterInfo] Add a method to set the size of a virtual register a po... | Quentin Colombet | 2016-03-07 | 1 | -0/+4 |
| * | [MachineRegisterInfo] Get rid of the global-isel ifdefs. | Quentin Colombet | 2016-03-07 | 1 | -6/+3 |
| * | [GlobalISel][MachineRegisterInfo] Add a method to create generic vregs. | Quentin Colombet | 2016-02-11 | 1 | -0/+16 |
| * | [GlobalISel] Remember the size of generic virtual registers | Quentin Colombet | 2016-02-10 | 1 | -0/+9 |
| * | Scheduler / Regalloc: use unique_ptr[] instead of std::vector | Fiona Glaser | 2015-12-02 | 1 | -4/+3 |
| * | Refactor: Simplify boolean conditional return statements in lib/CodeGen. | Rafael Espindola | 2015-10-24 | 1 | -5/+2 |
