| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [TargetRegisterInfo] Remove SVT argument from getCommonSubClass. | Craig Topper | 2019-09-13 | 1 | -13/+5 |
| * | Eliminate implicit Register->unsigned conversions in VirtRegMap. NFC | Daniel Sanders | 2019-08-13 | 1 | -1/+1 |
| * | Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re... | Daniel Sanders | 2019-08-01 | 1 | -14/+15 |
| * | Reland "[DwarfDebug] Dump call site debug info" | Djordje Todorovic | 2019-07-31 | 1 | -0/+13 |
| * | Revert "[DwarfDebug] Dump call site debug info" | Djordje Todorovic | 2019-07-12 | 1 | -14/+0 |
| * | [DwarfDebug] Dump call site debug info | Djordje Todorovic | 2019-07-09 | 1 | -0/+14 |
| * | [RegAlloc] Avoid compile time regression with multiple copy hints. | Jonas Paulsson | 2019-03-11 | 1 | -0/+6 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | Rename DEBUG macro to LLVM_DEBUG. | Nicola Zaghen | 2018-05-14 | 1 | -1/+2 |
| * | Remove \brief commands from doxygen comments. | Adrian Prantl | 2018-05-01 | 1 | -1/+1 |
| * | IWYU for llvm-config.h in llvm, additions. | Nico Weber | 2018-04-30 | 1 | -0/+1 |
| * | [MIR] Adding support for Named Virtual Registers in MIR. | Puyan Lotfi | 2018-03-30 | 1 | -4/+10 |
| * | Fix layering of MachineValueType.h by moving it from CodeGen to Support | David Blaikie | 2018-03-23 | 1 | -1/+1 |
| * | Re-commit: [MachineLICM] Add functions to MachineLICM to hoist invariant stores | Zaara Syeda | 2018-03-23 | 1 | -0/+23 |
| * | Revert [MachineLICM] This reverts commit rL327856 | Zaara Syeda | 2018-03-19 | 1 | -23/+0 |
| * | [MachineLICM] Add functions to MachineLICM to hoist invariant stores | Zaara Syeda | 2018-03-19 | 1 | -0/+23 |
| * | [GISel][NFC]: Move RegisterBankInfo::getSizeInBits into TargetRegisterInfo. | Aditya Nandakumar | 2018-02-02 | 1 | -0/+22 |
| * | Followup on Proposal to move MIR physical register namespace to '$' sigil. | Puyan Lotfi | 2018-01-31 | 1 | -3/+3 |
| * | MachineFunction: Return reference from getFunction(); NFC | Matthias Braun | 2017-12-15 | 1 | -5/+5 |
| * | [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. | Francis Visoiu Mistrih | 2017-12-07 | 1 | -0/+15 |
| * | [Regalloc] Generate and store multiple regalloc hints. | Jonas Paulsson | 2017-12-05 | 1 | -25/+30 |
| * | [CodeGen] Always use `printReg` to print registers in both MIR and debug | Francis Visoiu Mistrih | 2017-11-30 | 1 | -2/+5 |
| * | [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output | Francis Visoiu Mistrih | 2017-11-30 | 1 | -2/+2 |
| * | [CodeGen] Print register names in lowercase in both MIR and debug output | Francis Visoiu Mistrih | 2017-11-28 | 1 | -3/+5 |
| * | [CodeGen] Rename functions PrintReg* to printReg* | Francis Visoiu Mistrih | 2017-11-28 | 1 | -7/+7 |
| * | Fix a bunch more layering of CodeGen headers that are in Target | David Blaikie | 2017-11-17 | 1 | -3/+3 |
| * | [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints. | Jonas Paulsson | 2017-11-10 | 1 | -4/+5 |
| * | Move TargetFrameLowering.h to CodeGen where it's implemented | David Blaikie | 2017-11-03 | 1 | -1/+1 |
| * | Reverting r315590; it did not include changes for llvm-tblgen, which is causi... | Aaron Ballman | 2017-10-15 | 1 | -1/+1 |
| * | [dump] Remove NDEBUG from test to enable dump methods [NFC] | Don Hinton | 2017-10-12 | 1 | -1/+1 |
| * | TableGen support for parameterized register class information | Krzysztof Parzyszek | 2017-09-14 | 1 | -2/+5 |
| * | [Target] Fix some Clang-tidy modernize-use-using and Include What You Use war... | Eugene Zelenko | 2017-06-19 | 1 | -5/+15 |
| * | Sort the remaining #include lines in include/... and lib/.... | Chandler Carruth | 2017-06-06 | 1 | -1/+1 |
| * | BitVector: add iterators for set bits | Francis Visoiu Mistrih | 2017-05-17 | 1 | -2/+1 |
| * | Move value type list from TargetRegisterClass to TargetRegisterInfo | Krzysztof Parzyszek | 2017-04-24 | 1 | -3/+3 |
| * | Revert r301231: Accidentally committed stale files | Krzysztof Parzyszek | 2017-04-24 | 1 | -2/+2 |
| * | Move value type list from TargetRegisterClass to TargetRegisterInfo | Krzysztof Parzyszek | 2017-04-24 | 1 | -2/+2 |
| * | Move size and alignment information of regclass to TargetRegisterInfo | Krzysztof Parzyszek | 2017-04-24 | 1 | -5/+5 |
| * | Revert "Correct register pressure calculation in presence of subregs" | Stanislav Mekhanoshin | 2017-02-24 | 1 | -9/+0 |
| * | Correct register pressure calculation in presence of subregs | Stanislav Mekhanoshin | 2017-02-23 | 1 | -0/+9 |
| * | Cleanup dump() functions. | Matthias Braun | 2017-01-28 | 1 | -3/+3 |
| * | Add iterator_range<regclass_iterator> to {Target,MC}RegisterInfo, NFC | Krzysztof Parzyszek | 2017-01-25 | 1 | -6/+4 |
| * | Extract LaneBitmask into a separate type | Krzysztof Parzyszek | 2016-12-15 | 1 | -8/+2 |
| * | Clarify rules for reserved regs, fix aarch64 ones. | Matthias Braun | 2016-11-30 | 1 | -0/+30 |
| * | Use the range variant of find instead of unpacking begin/end | David Majnemer | 2016-08-11 | 1 | -1/+1 |
| * | MachineFunction: Return reference for getFrameInfo(); NFC | Matthias Braun | 2016-07-28 | 1 | -2/+2 |
| * | [TargetRegisterInfo] Re-apply r265734. | Quentin Colombet | 2016-04-08 | 1 | -12/+5 |
| * | Revert "[TargetRegisterInfo] Refactor the code to use BitMaskClassIterator." | Quentin Colombet | 2016-04-08 | 1 | -5/+12 |
| * | [TargetRegisterInfo] Refactor the code to use BitMaskClassIterator. | Quentin Colombet | 2016-04-07 | 1 | -12/+5 |
| * | ARM, AArch64, X86: Check preserved registers for tail calls. | Matthias Braun | 2016-04-04 | 1 | -0/+9 |
