| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Revert "[AMDGPU] Invert the handling of skip insertion." | Nicolai Hähnle | 2020-02-03 | 1 | -2/+0 |
| * | [AMDGPU] Invert the handling of skip insertion. | cdevadas | 2020-01-15 | 1 | -0/+2 |
| * | CMake: Make most target symbols hidden by default | Tom Stellard | 2020-01-14 | 1 | -1/+1 |
| * | [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. | Michael Liao | 2020-01-14 | 1 | -1/+1 |
| * | Sink all InitializePasses.h includes | Reid Kleckner | 2019-11-13 | 1 | -0/+1 |
| * | AMDGPU: Add default denormal mode to MachineFunctionInfo | Matt Arsenault | 2019-11-01 | 1 | -0/+2 |
| * | Revert "[AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs." | Jay Foad | 2019-10-10 | 1 | -3/+0 |
| * | AMDGPU: Use SGPR_128 instead of SReg_128 for vregs | Matt Arsenault | 2019-10-10 | 1 | -2/+2 |
| * | AMDGPU: Run AMDGPUCodeGenPrepare after scalar opts | Matt Arsenault | 2019-08-27 | 1 | -6/+5 |
| * | [llvm] Migrate llvm::make_unique to std::make_unique | Jonas Devlieghere | 2019-08-15 | 1 | -5/+5 |
| * | [AMDGPU] Printf runtime binding pass | Stanislav Mekhanoshin | 2019-08-12 | 1 | -0/+4 |
| * | [AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs. | Michael Liao | 2019-07-25 | 1 | -0/+3 |
| * | [AMDGPU] Add the adjusted FP as a livein register. | Michael Liao | 2019-07-16 | 1 | -25/+27 |
| * | AMDGPU: Serialize mode from MachineFunctionInfo | Matt Arsenault | 2019-07-10 | 1 | -0/+3 |
| * | AMDGPU: Make AMDGPUPerfHintAnalysis an SCC pass | Matt Arsenault | 2019-07-05 | 1 | -0/+2 |
| * | AMDGPU: Add pass to lower SGPR spills | Matt Arsenault | 2019-07-03 | 1 | -0/+4 |
| * | [AMDGPU] Enable serializing of argument info. | Michael Liao | 2019-07-03 | 1 | -0/+79 |
| * | [AMDGPU] LCSSA pass added in preISel. Uniform values defined in the divergent... | Alexander Timofeev | 2019-07-02 | 1 | -0/+1 |
| * | Rename ExpandISelPseudo->FinalizeISel, delay register reservation | Matt Arsenault | 2019-06-19 | 1 | -1/+2 |
| * | [AMDGPU] Propagate function attributes thru bitcasts | Stanislav Mekhanoshin | 2019-06-17 | 1 | -3/+4 |
| * | [AMDGPU] gfx1010 wavefrontsize intrinsic folding | Stanislav Mekhanoshin | 2019-06-17 | 1 | -1/+1 |
| * | [AMDGPU] Pass to propagate ABI attributes from kernels to the functions | Stanislav Mekhanoshin | 2019-06-17 | 1 | -4/+11 |
| * | Revert CMake: Make most target symbols hidden by default | Tom Stellard | 2019-06-11 | 1 | -1/+1 |
| * | CMake: Make most target symbols hidden by default | Tom Stellard | 2019-06-10 | 1 | -1/+1 |
| * | [AMDGPU] Create a TargetInfo header. NFC | Richard Trieu | 2019-05-14 | 1 | -0/+1 |
| * | [AMDGPU] gfx1010 GCNRegBankReassign pass | Stanislav Mekhanoshin | 2019-05-01 | 1 | -0/+2 |
| * | [AMDGPU] gfx1010 GCNNSAReassign pass | Stanislav Mekhanoshin | 2019-05-01 | 1 | -0/+15 |
| * | [GlobalISel] Introduce a CSEConfigBase class to allow targets to define their... | Amara Emerson | 2019-04-15 | 1 | -0/+6 |
| * | Reapply [ValueTracking] Support min/max selects in computeConstantRange() | Nikita Popov | 2019-04-07 | 1 | -2/+9 |
| * | [AMDGPU] Add MachineDCE pass after RenameIndependentSubregs | Stanislav Mekhanoshin | 2019-04-05 | 1 | -0/+9 |
| * | [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure. | Neil Henning | 2019-04-01 | 1 | -7/+5 |
| * | AMDGPU: Add additional MIR tests for exec mask optimizations | Matt Arsenault | 2019-03-27 | 1 | -3/+11 |
| * | CodeGen: Refactor regallocator command line and target selection | Matt Arsenault | 2019-03-19 | 1 | -6/+6 |
| * | [AMDGPU] Add an experimental buffer fat pointer address space. | Neil Henning | 2019-03-18 | 1 | -2/+3 |
| * | AMDGPU: Partially fix default device for HSA | Matt Arsenault | 2019-03-17 | 1 | -1/+2 |
| * | MIR: Allow targets to serialize MachineFunctionInfo | Matt Arsenault | 2019-03-14 | 1 | -0/+73 |
| * | AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) | Aakanksha Patil | 2019-03-07 | 1 | -1/+3 |
| * | AMDGPU: Fix typo | Matt Arsenault | 2019-02-28 | 1 | -1/+1 |
| * | AMDGPU: Enable function calls by default | Matt Arsenault | 2019-02-28 | 1 | -4/+9 |
| * | AMDGPU: Remove debugger related subtarget features | Matt Arsenault | 2019-02-21 | 1 | -2/+0 |
| * | [AMDGPU] Enable DPP combiner pass by default. | Valery Pykhtin | 2019-02-11 | 1 | -1/+1 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try | David Stuttard | 2019-01-14 | 1 | -0/+1 |
| * | Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attribute | Aakanksha Patil | 2018-12-13 | 1 | -3/+1 |
| * | [AMDGPU] Support for "uniform-work-group-size" attribute | Aakanksha Patil | 2018-12-12 | 1 | -1/+3 |
| * | [AMDGPU] Add new Mode Register pass | Tim Corringham | 2018-12-10 | 1 | -0/+9 |
| * | [Targets] Add errors for tiny and kernel codemodel on targets that don't supp... | David Green | 2018-12-07 | 1 | -7/+1 |
| * | [AMDGPU] Partial revert of rL348371: Turn on the DPP combiner by default | Valery Pykhtin | 2018-12-06 | 1 | -1/+1 |
| * | [AMDGPU]: Turn on the DPP combiner by default | Valery Pykhtin | 2018-12-05 | 1 | -1/+1 |
| * | [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) | Valery Pykhtin | 2018-11-30 | 1 | -0/+8 |
