| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [RISCV] Check the target-abi module flag matches the option | Zakk Chen | 2020-01-27 | 1 | -2/+12 |
| * | CMake: Make most target symbols hidden by default | Tom Stellard | 2020-01-14 | 1 | -1/+1 |
| * | [RISCV] Enable the machine outliner for RISC-V | lewis-revill | 2019-12-19 | 1 | -0/+3 |
| * | [RISCV] Add subtargets initialized with target feature | Zakk Chen | 2019-12-17 | 1 | -2/+25 |
| * | Sink all InitializePasses.h includes | Reid Kleckner | 2019-11-13 | 1 | -0/+1 |
| * | [RISCV GlobalISel] Adding initial GlobalISel infrastructure | Daniel Sanders | 2019-08-20 | 1 | -0/+29 |
| * | [llvm] Migrate llvm::make_unique to std::make_unique | Jonas Devlieghere | 2019-08-15 | 1 | -1/+1 |
| * | [RISCV] Add RISCV-specific TargetTransformInfo | Sam Elliott | 2019-06-21 | 1 | -1/+8 |
| * | Revert CMake: Make most target symbols hidden by default | Tom Stellard | 2019-06-11 | 1 | -1/+1 |
| * | CMake: Make most target symbols hidden by default | Tom Stellard | 2019-06-10 | 1 | -1/+1 |
| * | [RISCV] Create a TargetInfo header. NFC | Richard Trieu | 2019-05-15 | 1 | -0/+1 |
| * | [RISCV] Support -target-abi at the MC layer and for codegen | Alex Bradbury | 2019-03-09 | 1 | -1/+1 |
| * | [RISCV][NFC] Move some std::string to StringRef | Alex Bradbury | 2019-02-19 | 1 | -1/+1 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [Targets] Add errors for tiny and kernel codemodel on targets that don't supp... | David Green | 2018-12-07 | 1 | -7/+1 |
| * | [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A | Alex Bradbury | 2018-09-19 | 1 | -0/+10 |
| * | [RISCV] Add machine function pass to merge base + offset | Sameer AbuAsal | 2018-06-27 | 1 | -0/+5 |
| * | [RISCV] Codegen support for atomic operations on RV32I | Alex Bradbury | 2018-06-13 | 1 | -0/+6 |
| * | [RISCV] Use init_array instead of ctors for RISCV target, by default | Mandeep Singh Grang | 2018-03-24 | 1 | -1/+2 |
| * | [RISCV] Implement support for the BranchRelaxation pass | Alex Bradbury | 2018-01-10 | 1 | -0/+3 |
| * | [RISCV] Fix 64-bit data layout mismatch between backend and target description | Mandeep Singh Grang | 2017-11-16 | 1 | -1/+1 |
| * | [RISCV] Initial codegen support for ALU operations | Alex Bradbury | 2017-10-19 | 1 | -2/+24 |
| * | Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine" | Matthias Braun | 2017-10-12 | 1 | -3/+3 |
| * | TargetMachine: Merge TargetMachine and LLVMTargetMachine | Matthias Braun | 2017-10-12 | 1 | -3/+3 |
| * | Delete Default and JITDefault code models | Rafael Espindola | 2017-08-03 | 1 | -3/+10 |
| * | Sort the remaining #include lines in include/... and lib/.... | Chandler Carruth | 2017-06-06 | 1 | -1/+1 |
| * | TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFC | Matthias Braun | 2017-05-30 | 1 | -1/+1 |
| * | [RISCV] Fix RV32 datalayout string and ensure initAsmInfo is called | Alex Bradbury | 2017-02-14 | 1 | -2/+4 |
| * | [RISCV] Add stub backend | Alex Bradbury | 2016-11-01 | 1 | -0/+58 |
