| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [Scheduling][ARM] Consistently enable PostRA Machine scheduling | David Green | 2019-11-05 | 1 | -0/+4 |
| * | [Subtarget] Merge ProcSched and ProcDesc arrays in MCSubtargetInfo into a sin... | Craig Topper | 2019-03-05 | 1 | -2/+2 |
| * | [Subtarget] Create a separate SubtargetSubtargetKV struct for ProcDesc to rem... | Craig Topper | 2019-03-05 | 1 | -1/+1 |
| * | [AsmPrinter] Remove hidden flag -print-schedule. | Andrea Di Biagio | 2019-02-04 | 1 | -69/+1 |
| * | [MC][X86] Correctly model additional operand latency caused by transfer delay... | Andrea Di Biagio | 2019-01-23 | 1 | -2/+16 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [CodeGen] assume max/default throughput for unspecified instructions | Sanjay Patel | 2018-06-05 | 1 | -7/+5 |
| * | [MCSchedule] Add the ability to compute the latency and throughput informatio... | Andrea Di Biagio | 2018-05-31 | 1 | -2/+2 |
| * | [MC] Moved all the remaining logic that computed instruction latency and reci... | Andrea Di Biagio | 2018-04-15 | 1 | -2/+2 |
| * | [TargetSchedule] shrink interface for init(); NFCI | Sanjay Patel | 2018-04-08 | 1 | -2/+2 |
| * | [CodeGen] allow printing of zero latency in sched comments | Sanjay Patel | 2018-03-14 | 1 | -5/+3 |
| * | Introduce the "retpoline" x86 mitigation technique for variant #2 of the spec... | Chandler Carruth | 2018-01-22 | 1 | -0/+4 |
| * | AArch64: Fix emergency spillslot being out of reach for large callframes | Matthias Braun | 2018-01-19 | 1 | -0/+3 |
| * | Revert "AArch64: Fix emergency spillslot being out of reach for large callfra... | Matthias Braun | 2018-01-10 | 1 | -3/+0 |
| * | AArch64: Fix emergency spillslot being out of reach for large callframes | Matthias Braun | 2018-01-10 | 1 | -0/+3 |
| * | Fix a bunch more layering of CodeGen headers that are in Target | David Blaikie | 2017-11-17 | 1 | -1/+1 |
| * | Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering | David Blaikie | 2017-11-08 | 1 | -1/+1 |
| * | Add logic to greedy reg alloc to avoid bad eviction chains | Marina Yatsina | 2017-10-22 | 1 | -0/+4 |
| * | Support itineraries in TargetSubtargetInfo::getSchedInfoStr - Now if the give... | Andrew V. Tischenko | 2017-08-01 | 1 | -3/+10 |
| * | [Target] Fix some Clang-tidy modernize-use-using and Include What You Use war... | Eugene Zelenko | 2017-06-19 | 1 | -6/+8 |
| * | Sort the remaining #include lines in include/... and lib/.... | Chandler Carruth | 2017-06-06 | 1 | -1/+1 |
| * | This patch closes PR#32216: Better testing of schedule model instruction late... | Andrew V. Tischenko | 2017-04-14 | 1 | -0/+46 |
| * | TargetSubtargetInfo: Move implementation to lib/CodeGen; NFC | Matthias Braun | 2016-11-22 | 1 | -0/+54 |
