| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [RISCV64] Emit correct lib call for fp(float/double) to ui/si | Kamlesh Kumar | 2020-06-25 | 1 | -0/+34 |
| * | [RISCV] Support ABI checking with per function target-features | Zakk Chen | 2020-01-27 | 1 | -0/+14 |
| * | Revert "[RISCV] Support ABI checking with per function target-features" | Zakk Chen | 2020-01-27 | 1 | -14/+0 |
| * | [RISCV] Support ABI checking with per function target-features | Zakk Chen | 2020-01-15 | 1 | -0/+14 |
| * | Revert "[RISCV] Support ABI checking with per function target-features" | Zakk Chen | 2020-01-15 | 1 | -14/+0 |
| * | [RISCV] Support ABI checking with per function target-features | Zakk Chen | 2020-01-15 | 1 | -0/+14 |
| * | CodeGen: Use LLT instead of EVT in getRegisterByName | Matt Arsenault | 2020-01-09 | 1 | -1/+1 |
| * | Move tail call disabling code to target independent code | Reid Kleckner | 2020-01-03 | 1 | -4/+0 |
| * | [IR] Split out target specific intrinsic enums into separate headers | Reid Kleckner | 2019-12-11 | 1 | -0/+1 |
| * | [RISCV] Don't force Local Exec TLS for non-PIC | James Clarke | 2019-12-03 | 1 | -4/+1 |
| * | [RISCV] Implement the TargetLowering::getRegisterByName hook | Luís Marques | 2019-11-04 | 1 | -0/+19 |
| * | [RISCV] Lower llvm.trap and llvm.debugtrap | Sam Elliott | 2019-10-28 | 1 | -0/+3 |
| * | [RISCV] Add support for half-precision floats | Luís Marques | 2019-10-25 | 1 | -1/+6 |
| * | [RISCV] Add support for -ffixed-xX flags | Simon Cook | 2019-10-22 | 1 | -0/+38 |
| * | [RISCV] Support fast calling convention | Shiva Chen | 2019-10-15 | 1 | -2/+67 |
| * | [RISCV] Rename FPRs and use Register arithmetic | Luis Marques | 2019-09-27 | 1 | -36/+38 |
| * | [Alignment][NFC] Remove unneeded llvm:: scoping on Align types | Guillaume Chatelet | 2019-09-27 | 1 | -1/+1 |
| * | [RISCV] Fix static analysis issues | Luis Marques | 2019-09-20 | 1 | -2/+1 |
| * | [Alignment][NFC] Use Align with TargetLowering::setPrefFunctionAlignment | Guillaume Chatelet | 2019-09-06 | 1 | -2/+2 |
| * | [Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignment | Guillaume Chatelet | 2019-09-06 | 1 | -3/+3 |
| * | [LLVM][Alignment] Make functions using log of alignment explicit | Guillaume Chatelet | 2019-09-05 | 1 | -2/+2 |
| * | [RISCV] Enable tail call opt for variadic function | Jim Lin | 2019-09-04 | 1 | -5/+0 |
| * | [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall | Shiva Chen | 2019-08-28 | 1 | -0/+10 |
| * | Do a sweep of symbol internalization. NFC. | Benjamin Kramer | 2019-08-23 | 1 | -2/+2 |
| * | [RISCV] Convert registers from unsigned to Register | Luis Marques | 2019-08-16 | 1 | -12/+12 |
| * | [RISCV] Lower inline asm constraint A for RISC-V | Lewis Revill | 2019-08-16 | 1 | -0/+17 |
| * | [risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM | Daniel Sanders | 2019-08-12 | 1 | -18/+18 |
| * | [RISCV] Fix ICE in isDesirableToCommuteWithShift | Sam Elliott | 2019-08-12 | 1 | -2/+4 |
| * | [RISCV] Allow ABI Names in Inline Assembly Constraints | Sam Elliott | 2019-08-08 | 1 | -34/+78 |
| * | [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions | Shiva Chen | 2019-08-06 | 1 | -0/+24 |
| * | [LLVM][Alignment] Introduce Alignment Type | Guillaume Chatelet | 2019-08-05 | 1 | -1/+1 |
| * | Emit diagnostic if an inline asm constraint requires an immediate | Bill Wendling | 2019-08-03 | 1 | -0/+4 |
| * | [RISCV] Support 'f' Inline Assembly Constraint | Sam Elliott | 2019-07-31 | 1 | -0/+21 |
| * | [RISCV] Add support for lowering floating point inlineasm clobbers | Simon Cook | 2019-07-31 | 1 | -0/+46 |
| * | [RISCV] Reset NoPHIS MachineFunctionProperty in emitSelectPseudo | Alex Bradbury | 2019-07-18 | 1 | -0/+1 |
| * | [RISCV] Fix ICE in isDesirableToCommuteWithShift | Sam Elliott | 2019-07-09 | 1 | -1/+1 |
| * | [RISCV] Specify registers used in DWARF exception handling | Alex Bradbury | 2019-07-08 | 1 | -0/+10 |
| * | [RISCV] Support @llvm.readcyclecounter() Intrinsic | Sam Elliott | 2019-07-05 | 1 | -0/+86 |
| * | [RISCV] Add lowering of global TLS addresses | Lewis Revill | 2019-06-19 | 1 | -0/+114 |
| * | [RISCV] Prevent re-ordering some adds after shifts | Sam Elliott | 2019-06-18 | 1 | -0/+45 |
| * | [RISCV] Lower calls through PLT | Lewis Revill | 2019-06-18 | 1 | -4/+14 |
| * | [RISCV] Add lowering of addressing sequences for PIC | Lewis Revill | 2019-06-11 | 1 | -11/+19 |
| * | [RISCV] Lower inline asm constraints I, J & K for RISC-V | Lewis Revill | 2019-06-11 | 1 | -0/+38 |
| * | [RISCV] Support Bit-Preserving FP in F/D Extensions | Sam Elliott | 2019-06-07 | 1 | -0/+5 |
| * | [RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS | Luis Marques | 2019-04-16 | 1 | -3/+100 |
| * | Test commit: Remove double variable assignment | Lewis Revill | 2019-04-03 | 1 | -1/+1 |
| * | [RISCV] Attach VK_RISCV_CALL to symbols upon creation | Alex Bradbury | 2019-04-01 | 1 | -2/+4 |
| * | [RISCV] Generate address sequences suitable for mcmodel=medium | Alex Bradbury | 2019-04-01 | 1 | -35/+53 |
| * | [RISCV] Add seto pattern expansion | Luis Marques | 2019-04-01 | 1 | -3/+3 |
| * | [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float... | Alex Bradbury | 2019-03-30 | 1 | -15/+92 |
