| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [AMDGPU] Add handling of 160 bit registers in analyzeResourceUsage | Stanislav Mekhanoshin | 2019-11-06 | 1 | -0/+28 |
| * | [AMDGPU] Created a sub-register class for the return address operand in the r... | Christudasan Devadasan | 2019-07-09 | 1 | -11/+11 |
| * | AMDGPU: Make s34 the FP register | Matt Arsenault | 2019-07-08 | 1 | -13/+13 |
| * | AMDGPU: Always use s33 for global scratch wave offset | Matt Arsenault | 2019-06-20 | 1 | -13/+13 |
| * | AMDGPU: Fix unreachable when counting register usage of SGPR96 | Matt Arsenault | 2019-04-15 | 1 | -0/+13 |
| * | AMDGPU: Enable function calls by default | Matt Arsenault | 2019-02-28 | 1 | -2/+2 |
| * | AMDGPU: Enable code object v3 for AMDHSA only | Konstantin Zhuravlyov | 2018-11-15 | 1 | -3/+3 |
| * | Revert r345542: AMDGPU: Enable code object v3 by default | Konstantin Zhuravlyov | 2018-10-30 | 1 | -3/+3 |
| * | AMDGPU: Enable code object v3 by default | Konstantin Zhuravlyov | 2018-10-29 | 1 | -3/+3 |
| * | AMDGPU: Increase default stack alignment | Matt Arsenault | 2018-03-29 | 1 | -4/+4 |
| * | [AMDGPU] Switch to the new addr space mapping by default | Yaxun Liu | 2018-02-02 | 1 | -8/+8 |
| * | AMDGPU: Enable IPRA | Matt Arsenault | 2017-11-28 | 1 | -3/+3 |
| * | AMDGPU: Remove error on calls for amdgcn | Matt Arsenault | 2017-08-03 | 1 | -3/+3 |
| * | AMDGPU: Fix clobbering CSR VGPRs when spilling SGPR to it | Matt Arsenault | 2017-08-02 | 1 | -4/+4 |
| * | AMDGPU: Analyze callee resource usage in AsmPrinter | Matt Arsenault | 2017-08-02 | 1 | -0/+230 |
