Instead of performing decisions inside the single aeshash() function, we have three implementations instead. Those decisions are permanent for each CPU, so the branch predictor should be pretty good, but hashing is somewhat performance-sensitive. We're only adding three of the four possible combinations of AVX512VL and VAES. Excluded from the implementation are the CPUs that support AVX512 but not VAES, which are the Skylake-based ones. Those are mostly found in server CPUs (Intel Xeon Scalable line) as well as top-end workstations (Intel Core i9), but never made into general desktop and laptop parts. For those, the performance will remain what it was in Qt 6.3. VAES is supported in Intel architectures codenamed Sunny Cove and Gracemont and their successors. That means it's supported in both the E and P cores of the Intel Alder Lake (12th Generation Core), as well as future Atom lines. But neither Atoms nor hybrid CPUS have AVX512 (at least when the E cores are active). AVX512+VAES is supported for Ice Lake (10th Generation Core), Tiger Lake (11th) as well as later generation with AVX512 support enabled. Like in qstring.cpp, we restricted ourselves to 256-bit operations, which don't cause performance impact and because the 512-bit VAESENC operates on the fused Ports 0 and 1, so it has the exact same throughput as two 256-bit VAESENC. Change-Id: I6fcda969a9e9427198bffffd16cece9c37dbdbd3 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>