diff options
| author | Allan Sandfeld Jensen <allan.jensen@qt.io> | 2024-10-01 12:06:14 +0200 |
|---|---|---|
| committer | Allan Sandfeld Jensen <allan.jensen@qt.io> | 2024-10-02 08:33:13 +0200 |
| commit | 3de914eef55351e2e7395a8e8ae57553f6218516 (patch) | |
| tree | fe74614e21f217d1f07304e4abc8910d6004dfdd /src/corelib | |
| parent | 0f20feea2112c2391e274dc4e81aa38a738b7023 (diff) | |
Add ARM SVE detection
Limited to ARM64 and little-endian to keep our code simple.
Change-Id: Ie65f71a31ca98d6929561d4b2ee1e9332b3a82d8
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Diffstat (limited to 'src/corelib')
| -rw-r--r-- | src/corelib/global/qsimd.cpp | 18 | ||||
| -rw-r--r-- | src/corelib/global/qsimd_p.h | 7 |
2 files changed, 23 insertions, 2 deletions
diff --git a/src/corelib/global/qsimd.cpp b/src/corelib/global/qsimd.cpp index 28d25b5baca..b4fff814e6c 100644 --- a/src/corelib/global/qsimd.cpp +++ b/src/corelib/global/qsimd.cpp @@ -49,6 +49,7 @@ // copied from <asm/hwcap.h> (Aarch64) #define HWCAP_AES (1 << 3) #define HWCAP_CRC32 (1 << 7) +#define HWCAP_SVE (1 << 22) // copied from <linux/auxvec.h> #define AT_HWCAP 16 /* arch dependent hints at CPU capabilities */ @@ -75,13 +76,15 @@ uint arraysize(T (&)[N]) neon crc32 aes + sve */ static const char features_string[] = "\0" " neon\0" " crc32\0" - " aes\0"; -static const int features_indices[] = { 0, 1, 7, 14 }; + " aes\0" + " sve\0"; +static const int features_indices[] = { 0, 1, 7, 14, 19 }; #elif defined(Q_PROCESSOR_MIPS) /* Data: dsp @@ -118,6 +121,8 @@ static inline quint64 detectProcessorFeatures() features |= CpuFeatureCRC32; if (auxvHwCap & HWCAP_AES) features |= CpuFeatureAES; + if (auxvHwCap & HWCAP_SVE) + features |= CpuFeatureSVE; # else // For ARM32: if (auxvHwCap & HWCAP_NEON) @@ -156,6 +161,12 @@ static inline quint64 detectProcessorFeatures() if (sysctlbyname("hw.optional.arm.FEAT_AES", &feature, &len, nullptr, 0) == 0) features |= feature ? CpuFeatureAES : 0; #endif +#if defined(__ARM_FEATURE_SVE) + features |= CpuFeatureSVE; +#else + if (sysctlbyname("hw.optional.arm.FEAT_SVE", &feature, &len, nullptr, 0) == 0) + features |= feature ? CpuFeatureSVE : 0; +#endif return features; #elif defined(Q_OS_WIN) && defined(Q_PROCESSOR_ARM_64) features |= CpuFeatureNEON; @@ -174,6 +185,9 @@ static inline quint64 detectProcessorFeatures() #if defined(__ARM_FEATURE_CRYPTO) features |= CpuFeatureAES; #endif +#if defined(__ARM_FEATURE_SVE) + features |= CpuFeatureSVE; +#endif return features; } diff --git a/src/corelib/global/qsimd_p.h b/src/corelib/global/qsimd_p.h index b613e04985e..99786d92a0c 100644 --- a/src/corelib/global/qsimd_p.h +++ b/src/corelib/global/qsimd_p.h @@ -347,12 +347,15 @@ inline uint32x4_t qvsetq_n_u32(uint32_t a, uint32_t b, uint32_t c, uint32_t d) #if defined(Q_CC_CLANG) #define QT_FUNCTION_TARGET_STRING_AES "crypto" #define QT_FUNCTION_TARGET_STRING_CRC32 "crc" +#define QT_FUNCTION_TARGET_STRING_SVE "sve" #elif defined(Q_CC_GNU) #define QT_FUNCTION_TARGET_STRING_AES "+crypto" #define QT_FUNCTION_TARGET_STRING_CRC32 "+crc" +#define QT_FUNCTION_TARGET_STRING_SVE "+sve" #elif defined(Q_CC_MSVC) #define QT_FUNCTION_TARGET_STRING_AES #define QT_FUNCTION_TARGET_STRING_CRC32 +#define QT_FUNCTION_TARGET_STRING_SVE #endif #elif defined(Q_PROCESSOR_ARM_32) #if defined(Q_CC_CLANG) @@ -372,6 +375,7 @@ enum CPUFeatures { CpuFeatureCRC32 = 4, CpuFeatureAES = 8, CpuFeatureARM_CRYPTO = CpuFeatureAES, + CpuFeatureSVE = 16, #elif defined(Q_PROCESSOR_MIPS) CpuFeatureDSP = 2, CpuFeatureDSPR2 = 4, @@ -395,6 +399,9 @@ static const uint64_t qCompilerCpuFeatures = 0 | CpuFeatureAES #endif #endif // Q_OS_LINUX && Q_PROCESSOR_ARM64 +#if defined(__ARM_FEATURE_SVE) && defined(Q_PROCESSOR_ARM_64) + | CpuFeatureSVE +#endif #if defined __mips_dsp | CpuFeatureDSP #endif |