Only sequential statements are allowed inside a process statement. An architecture statement part is comprised of zero or more concurrent statements. rtl appears to be the name of architecture and a process statement is a concurrent statement.
Notice from your referenced code you are having problems with:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity circularshift is port (
sn : in std_logic_vector(5 downto 1); -- number of rotate steps
di : in std_logic_vector(32 downto 1); -- data in
encdec : in std_logic ; -- enc or dec
do : out std_logic_vector(32 downto 1) -- data out
);
end circularshift;
architecture Behavioral of circularshift is
signal d0 : std_logic_vector(32 downto 1);
signal d1 : std_logic_vector(32 downto 1);
signal d2 : std_logic_vector(32 downto 1);
signal d3 : std_logic_vector(32 downto 1);
signal d4 : std_logic_vector(32 downto 1);
signal r1 : std_logic_vector(32 downto 1);
signal r2 : std_logic_vector(32 downto 1);
signal r4 : std_logic_vector(32 downto 1);
signal r8 : std_logic_vector(32 downto 1);
signal d5 : std_logic_vector(32 downto 1);
signal r16 : std_logic_vector(32 downto 1);
begin
p1 : process (encdec)
begin
if encdec <= '1' then
r1 <= d0(32-1 downto 1) & d0(32);
r2 <= d1(32-2 downto 1) & d1(32 downto 32-1);
r4 <= d2(32-4 downto 1) & d2(32 downto 32-3);
r8 <= d3(32-8 downto 1) & d3(32 downto 32-7);
r16 <= d4(32-16 downto 1) & d4(32 downto 32-15);
d0 <= di;
d1 <= r1 when (sn(1)='1') else d0;
d2 <= r2 when (sn(2)='1') else d1;
d3 <= r4 when (sn(3)='1') else d2;
d4 <= r8 when (sn(4)='1') else d3;
d5 <= r16 when (sn(5)='1') else d4;
do <= d5;
else
r1 <= d0(1) & d0(32 downto 2 );
r2 <= d1(2 downto 1) & d1(32 downto 3);
r4 <= d2(4 downto 1) & d2(32 downto 5);
r8 <= d3(8 downto 1) & d3(32 downto 9);
r16 <= d4(16 downto 1) & d4(32 downto 17);
d0 <= di;
d1 <= r1 when (sn(1)='1') else d0;
d2 <= r2 when (sn(2)='1') else d1;
d3 <= r4 when (sn(3)='1') else d2;
d4 <= r8 when (sn(4)='1') else d3;
d5 <= r16 when (sn(5)='1') else d4;
do <= d5;
end if;
end process;
end Behavioral;
-- I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim )
-- When I run check syntax, the following is displayed:
-- Compiling vhdl file "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" in Library work.
-- ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 38. parse error, unexpected WHEN, expecting SEMICOLON
-- ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 39. parse error, unexpected WHEN, expecting SEMICOLON
-- ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 40. parse error, unexpected WHEN, expecting SEMICOLON
-- ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 41. parse error, unexpected WHEN, expecting SEMICOLON
-- ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 42. parse error, unexpected WHEN, expecting SEMICOLON
-- ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 49. parse error, unexpected WHEN, expecting SEMICOLON
-- ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 50. parse error, unexpected WHEN, expecting SEMICOLON
-- ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 51. parse error, unexpected WHEN, expecting SEMICOLON
-- ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 52. parse error, unexpected WHEN, expecting SEMICOLON
-- ERROR:HDLParsers:164 - "C:/Xilinx/rcc2/rc5pi/circularshift.vhd" Line 53. parse error, unexpected WHEN, expecting SEMICOLON
That the line you ask about in your question is line 54:
d3 <= r4 when (sn(3)='1') else d2;
And that this a concurrent signal assignment and yet it is showing up in a process statement (the domain of sequential statements).
The form of this is a 'conditional signal assignment', which happens to have been added to sequential signal assignments by IEEE Std 1076-2008 (10.5.3 Conditional signal assignments, § 10 is entitled Sequential statements).
And from this we can infer that while Modelsim supports the 2008 VHDL standard, your XST doesn't (error messages of the form 'ERROR:HDLParsers:' are XST messages).
If and when Xilinx would support synthesis of conditional signal assignment statements within a process (as sequential signal assignment) is a matter of versions and/or policy. There's no particular difference in difficulty of synthesis to support it, while representing significant change in the parser.
VHDL is case insensitive except in extended identifiers and character literals.
From IEEE Std 1076-2008 15.2 Character set:
The only characters allowed in the text of a VHDL description (except
within comments—see 15.9, and within text treated specially due to the
effect of tool directives—see 15.11) are the graphic characters and
format effectors. Each graphic character corresponds to a unique code
of the ISO eight-bit coded character set (ISO/IEC 8859-1:1998) and is
represented (visually) by a graphical symbol.
basic_graphic_character ::=
upper_case_letter | digit | special_character | space_character
graphic_character ::=
basic_graphic_character | lower_case_letter | other_special_character
basic_character ::=
basic_graphic_character | format_effector
The basic character set is sufficient for writing any description,
other than a PSL declaration, a PSL directive, or a PSL verification
unit.
And 15.4 Identifiers:
All characters of a basic identifier are significant, including any
underline character inserted between a letter or digit and an adjacent
letter or digit. Basic identifiers differing only in the use of
corresponding uppercase and lowercase letters are considered the same.
addendum
Thanks a lot for the answer, how about the Inside_process vs
Outside_process ? Out_signal <= signal1 and (not signal2); Out_signal
is being assigned once inside and once outside, but the result doesn't
change, circuit still works, no warnings? So is this a sequential
assignment or concurrent? If concurrent, how can it be inside the
process, if sequential, how can it be outside the process? – Anarkie
6 hours ago
There's an obvious difference between the two processes. The one with the concurrent signal assignment(Outside_process) will have Out_signal show change immediately upon change update for signals signal1 and signal2 because the concurrent signal assignment will have an equivalent process containing a sequential signal assignment statement and a sensitivity list equivalent containing signal1 and signal2. (Every signal appearing on the right hand side of a signal assignment statement).
The process Inside_process only has clk in the sensitivity list, meaning in simulation Out_signal will be assigned at the next clk'EVENT, an apparent half clock delay because the assignments to your two shift register signals are visible in the next delta cycle.
See this stackoverflow answer The VHDL Simulation Cycle as well as this one - Unexpected delays with register VHDL.
Interestingly enough both will probably synthesize identically because the sensitivity list will either be disregarded or updated (assumed to include signal1 and signal2 in Inside_process). Any assumptions should likely show up in warnings.
Elaboration devolves a design description into block statements (maintaining hierarchy), process statements and function calls. All concurrent statements have a process statement equivalent, potentially within block statements (or nested block statements). In the case of simple signal assignment statements there is little observable difference between signal assignment inside or outside a process (except the sensitivity list which in this case is incomplete for Inside_process).
A design specification will be elaborated before simulation and as a predicate for synthesis as well.
