Verilog: cannot be driven by primitives or continuous assignment

Could someone help me figure out why I am getting such an error. The code below implements a 4 bit shift register adder which takes one bit at a time from each register computes the sum of the 2 bits using a full adder stores the carry (previous) and then pushes the result of the full adder back to first shift register.thus at the end of 4 clock cycles the result (sum) is in the first register

Error i am getting Reg cannot be driven by primitives or continuous assignment.

CODE:

module FADDER(s,c,x,y,z);
    input x,y,z;
    output s,c;
    reg s,c;

    always @(x or y or z)
    begin
        s = (x^y)^z;
        c = (x & y) | (y & z) | (z & x);
    end 
endmodule

module shift_reg_add(a, b,clr, clk);
    output [3:0] a,b;
    reg [3:0] a,b;
    input clr, clk;

    reg carr = 1'b0;
    wire w1, newcarr;
    wire w2,w3;

    assign w2 = a[0];
    assign w3 = b[0];
    FADDER f(w1, newcarr, w2, w3, carr);

    always @(posedge clk) begin
        a <= {1'b0, a[3:1]};
        a[3] <= w1;
        b <= {1'b0, b[3:1]};
        carr <= newcarr; 
    end
endmodule

module testbench;
    reg [3:0] a,b;
    reg clr, clk;

    shift_reg_add s1(a,b,clr,clk);

    initial begin
        clk = 0;
        clr = 1;
    end

    always begin
        #2 clk = ~clk;
    end

    initial $monitor($time, " clr %b a = %b b = %b prev_carr = %b", clr, a, b, s1.carr);

    initial begin
        a = 4'b0101;
        b = 4'b1100;
        clr = 1'b1;
    end
endmodule