Additional bits computation in VHDL

Given an array of N elements, element is M bits vector. I am going to sum them up.

For example, given an array of 12 bits vectors.

type data_array is array (integer range 0 to 68)  of std_logic_vector( 11 downto 0); --69s 12-bits-vectors 

To sum up, I use two loops:

• first loop: create an array data_array_sum_1 of 6 elements: sum each 10 vectors ( 10 * 6) + sum 9 vectors up.
• second loop: sum 6 elements up, data_array_sum_2

data_array_sum_1 will be created as:

 type data_array_sum_1 is array (integer range 0 to 6)  of signed ( 11+3 downto 0);

I add log2(10)=3 additional bits.

data_array_sum_2 will be created as:

 type data_array_sum_2 is  std_logic_vector ( 11+ 5 downto 0);

I add log2(6)=2 additional bits to data_array_sum_1. data_array_sum_2 is the result of addition of 69 elements.

If I don't use loops and sum them up, I should add log2(69)=6, that means the result of addition of 69 elements are 18 bits vector.

I think, I should get the same length of the resultant vector and the length doesn't depend on the algorithm of addition, right? Have I mistaken?

EDIT 1

I am checking different options to sum up two std_logic_vectors. I have read in this forum you suggest to use signed or unsigned type to add them.

My design file:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity test is
port (
    a       : in std_logic_vector (11 downto 0);     
    b       : in std_logic_vector (11 downto 0);    

    result1 : out unsigned (12 downto 0);    
    result2 : out std_logic_vector (11 downto 0);
    result3 : out std_logic_vector (11 downto 0)
);

end test;

architecture Behavioral of test is 
signal f: std_logic_vector(12 downto 0);
begin
    result1 <= '0'& unsigned(a) + unsigned(b);
    f <=  std_logic_vector(unsigned(a) + unsigned(b));
    result3 <= f(12 downto 1);
    result2 <= std_logic_vector(signed(a) + signed(b));    

    --result3 <= std_logic_vector(('0'& a) + ( '0' & b)); 
    --result3 <= std_logic_vector(resize( a, a'length+1) + resize(b, b'length+1));

end Behavioral;

My test bench file:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
ENTITY testtb IS
END testtb;
 
ARCHITECTURE behavior OF testtb IS 
 
    COMPONENT test
    PORT(
         a : IN  std_logic_vector(11 downto 0);
         b : IN  std_logic_vector(11 downto 0);
         result1 : OUT  unsigned(12 downto 0);
         result3 : OUT  std_logic_vector(11 downto 0);
         result2 : OUT  std_logic_vector(11 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal a : std_logic_vector(11 downto 0) := (others => '0');
   signal b : std_logic_vector(11 downto 0) := (others => '0');

    --Outputs
   signal result1 : unsigned(12 downto 0);
   signal result2 : std_logic_vector(11 downto 0);
   signal result3 : std_logic_vector(11 downto 0);

 
BEGIN
 

   uut: test PORT MAP (
          a => a,
          b => b,
          result1 => result1,
          result2 => result2
        );


   stim_proc: process
   begin        

       a <= "001001010001";
       b <= "110110101111";
       wait for 10 ns;
       b <= "001001010001";
       a <= "110110101111";

    wait;
 end process;

 END;

I found the correct answer gives result1. Then I have added result3 with f and smth is wrong with f.

ERROR: Array sizes do not match.

Why has it happend? I add two vectors, it means I have one additional bit.