diff options
| author | Shawn Lin <shawn.lin@rock-chips.com> | 2025-11-12 18:53:18 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-11-13 06:17:23 -0600 |
| commit | 921b3f59b7b00cd7067ab775b0e0ca4eca436c2f (patch) | |
| tree | 07a1917305c4b6a8595434624c7cb7041ffa5e12 /drivers | |
| parent | 823576c894d73255d35c0d0dabbb6ffecf1f2667 (diff) | |
| download | net-921b3f59b7b00cd7067ab775b0e0ca4eca436c2f.tar.gz | |
PCI/ASPM: Avoid L0s and L1 on Hi1105 [19e5:1105] Wi-Fi
This Wi-Fi advertises the L0s and L1 capabilities but actually it doesn't
support them. This is confirmed by HiSilicon team in actual productization.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/1762916319-139532-1-git-send-email-shawn.lin@rock-chips.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/quirks.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 90f6abdb77f4d4..b9c252aa6fe08a 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2525,6 +2525,7 @@ static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1); /* * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain |