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| author | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-06-15 08:50:22 +0200 |
|---|---|---|
| committer | Jonathan Corbet <corbet@lwn.net> | 2020-06-19 14:10:13 -0600 |
| commit | 781885fdf09f55ff14172749258f7380f859f2ba (patch) | |
| tree | 7483ad342215ce587933882bdc2b6c2aefc2f394 | |
| parent | 7539b417626e5d5db132859678284e690771c499 (diff) | |
| download | linux-781885fdf09f55ff14172749258f7380f859f2ba.tar.gz | |
docs: sh: convert register-banks.txt to ReST
- Add a SPDX header;
- Adjust document title to follow ReST style;
- Add blank lines to make ReST markup happy
- Add it to sh/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/adf117cf1edd7f43cb839ff2800f4315dfbcce13.1592203650.git.mchehab+huawei@kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
| -rw-r--r-- | Documentation/sh/index.rst | 1 | ||||
| -rw-r--r-- | Documentation/sh/register-banks.rst (renamed from Documentation/sh/register-banks.txt) | 13 | ||||
| -rw-r--r-- | arch/sh/Kconfig.cpu | 2 |
3 files changed, 12 insertions, 4 deletions
diff --git a/Documentation/sh/index.rst b/Documentation/sh/index.rst index 967acad9ff5e99..b5933fd399f3be 100644 --- a/Documentation/sh/index.rst +++ b/Documentation/sh/index.rst @@ -8,6 +8,7 @@ SuperH Interfaces Guide :maxdepth: 1 new-machine + register-banks Memory Management ================= diff --git a/Documentation/sh/register-banks.txt b/Documentation/sh/register-banks.rst index a6719f2f65941f..2bef5c8fcbbc06 100644 --- a/Documentation/sh/register-banks.txt +++ b/Documentation/sh/register-banks.rst @@ -1,5 +1,8 @@ - Notes on register bank usage in the kernel - ========================================== +.. SPDX-License-Identifier: GPL-2.0 + +========================================== +Notes on register bank usage in the kernel +========================================== Introduction ------------ @@ -23,11 +26,15 @@ Presently the kernel uses several of these registers. - r0_bank, r1_bank (referenced as k0 and k1, used for scratch registers when doing exception handling). + - r2_bank (used to track the EXPEVT/INTEVT code) + - Used by do_IRQ() and friends for doing irq mapping based off of the interrupt exception vector jump table offset + - r6_bank (global interrupt mask) + - The SR.IMASK interrupt handler makes use of this to set the interrupt priority level (used by local_irq_enable()) - - r7_bank (current) + - r7_bank (current) diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu index 97ca35f2cd3738..fff419f3d7574c 100644 --- a/arch/sh/Kconfig.cpu +++ b/arch/sh/Kconfig.cpu @@ -85,7 +85,7 @@ config CPU_HAS_SR_RB that are lacking this bit must have another method in place for accomplishing what is taken care of by the banked registers. - See <file:Documentation/sh/register-banks.txt> for further + See <file:Documentation/sh/register-banks.rst> for further information on SR.RB and register banking in the kernel in general. config CPU_HAS_PTEAEX |