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| author | Vladimir Zapolskiy <vz@mleia.com> | 2025-09-04 21:46:42 +0300 |
|---|---|---|
| committer | Vladimir Zapolskiy <vz@mleia.com> | 2025-09-11 03:30:26 +0300 |
| commit | 65ae9ea77e1f2a20ad2866f99596df7ccdbd3b95 (patch) | |
| tree | 939e2be3316ca33c15065bb906352b3266731b4d /arch/arm | |
| parent | b17b850da6f9c4440a49d96cded5faa85123aadf (diff) | |
| download | linux-65ae9ea77e1f2a20ad2866f99596df7ccdbd3b95.tar.gz | |
ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells
Since commit 4cd2f417a0ac ("dt-bindings: pwm: Convert lpc32xx-pwm.txt
to yaml format") both types of PWM controlles on NXP LPC32xx SoC
fairly gained 3 cells, reflect it in the platform dtsi file.
The change removes a dt binding checker warning:
mpwm@400e8000: #pwm-cells:0:0: 3 was expected
Cc: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 6cf405e9b08260..916ab38f0a4c6c 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -301,8 +301,8 @@ mpwm: mpwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + #pwm-cells = <3>; status = "disabled"; - #pwm-cells = <2>; }; }; |