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authorDharma Balasubiramani <dharma.b@microchip.com>2025-09-15 14:43:57 +0530
committerNicolas Ferre <nicolas.ferre@microchip.com>2025-09-22 18:20:34 +0200
commitc656932c3ece3eebe6240bb20e5c1d8aa0d7ecb0 (patch)
treebfc00627fa75424e420a5a48a686bd1d7dbaf496 /arch/arm
parent82ab67d762e922bb5df1cbb442e8d4f12c26a7ae (diff)
downloadlinux-c656932c3ece3eebe6240bb20e5c1d8aa0d7ecb0.tar.gz
ARM: dts: microchip: sam9x7: Add qspi controller
Add support for QSPI controller. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Link: https://lore.kernel.org/r/20250915-sam9x7-qspi-dtsi-v1-1-1cc9adba7573@microchip.com Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/microchip/sam9x7.dtsi21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi
index 66c07e642c3e1a..46dacbbd201ddb 100644
--- a/arch/arm/boot/dts/microchip/sam9x7.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi
@@ -271,6 +271,27 @@
status = "disabled";
};
+ qspi: spi@f0014000 {
+ compatible = "microchip,sam9x7-ospi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xf0014000 0x100>, <0x60000000 0x20000000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(26))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(27))>;
+ dma-names = "tx", "rx";
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>;
+ clock-names = "pclk", "gclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 35>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_PLLADIV2>;
+ status = "disabled";
+ };
+
i2s: i2s@f001c000 {
compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc";
reg = <0xf001c000 0x100>;