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path: root/drivers/cxl/pci.c
AgeCommit message (Expand)AuthorFilesLines
2025-06-30cxl/pci: Replace mutex_lock_io() w mutex_lock() for mailbox accessAlison Schofield1-1/+1
2025-04-18cxl: Fix devm host device for CXL fwctl initializationDave Jiang1-1/+1
2025-04-02Merge tag 'cxl-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds1-1/+6
2025-03-17cxl: Add FWCTL support to CXLDave Jiang1-0/+4
2025-03-17Merge branch 'for-6.15/features' into cxl-for-nextDave Jiang1-0/+4
2025-02-26cxl: Add Get Supported Features command for kernel usageDave Jiang1-0/+4
2025-02-04cxl: Introduce 'struct cxl_dpa_partition' and 'struct cxl_range_info'Dan Williams1-1/+6
2025-01-22cxl/core/regs: Refactor out functions to count regblocks of given typeHuaisheng Ye1-1/+5
2024-12-10cxl/pci: Check dport->regs.rcd_pcie_cap availability before accessingLi Ming1-0/+3
2024-12-10cxl/pci: Fix potential bogus return value upon successful probingDavidlohr Bueso1-2/+1
2024-12-02module: Convert symbol namespace to string literalPeter Zijlstra1-1/+1
2024-11-08Merge branch 'cxl/for-6.13/dcd-prep' into cxl-for-nextDave Jiang1-4/+4
2024-11-08cxl/pci: Delay event buffer allocationIra Weiny1-4/+4
2024-10-28cxl/pci: Add sysfs attribute for CXL 1.1 device link statusKobayashi,Daisuke1-0/+78
2024-10-28cxl/core/regs: Add rcd_pcie_cap initializationKobayashi,Daisuke1-6/+19
2024-10-02move asm/unaligned.h to linux/unaligned.hAl Viro1-1/+1
2024-09-12cxl: Convert cxl_internal_send_cmd() to use 'struct cxl_mailbox' as inputDave Jiang1-2/+4
2024-09-12cxl: Move mailbox related bits to the same contextDave Jiang1-26/+52
2024-09-03cxl/port: Use __free() to drop put_device() for cxl_portLi Ming1-5/+2
2024-07-02cxl: add missing MODULE_DESCRIPTION() macrosJeff Johnson1-0/+1
2024-05-21Merge tag 'pci-v6.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds1-1/+23
2024-05-08cxl: Add post-reset warning if reset results in loss of previously committed ...Dave Jiang1-0/+22
2024-05-08PCI/CXL: Move CXL Vendor ID to pci_ids.hDave Jiang1-1/+1
2024-05-01cxl/pci: Process CPER eventsIra Weiny1-1/+70
2024-02-20acpi/ghes: Remove CXL CPER notificationsDan Williams1-56/+1
2024-01-22cxl/pci: Skip irq features if MSI/MSI-X are not supportedIra Weiny1-11/+15
2024-01-09cxl/pci: Register for and process CPER eventsIra Weiny1-1/+57
2023-10-31Merge branch 'for-6.7/cxl' into cxl/nextDan Williams1-1/+4
2023-10-31Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams1-8/+6
2023-10-27cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter1-1/+1
2023-10-27cxl/pci: Remove Component Register base address from struct cxl_dev_stateRobert Richter1-3/+0
2023-10-27cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_s...Robert Richter1-4/+5
2023-10-27cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter1-1/+1
2023-10-06cxl/memdev: Fix sanitize vs decoder setup lockingDan Williams1-0/+5
2023-10-06cxl/pci: Fix sanitize notifier setupDan Williams1-0/+4
2023-10-06cxl/pci: Clarify devm host for memdev relative setupDan Williams1-2/+2
2023-10-06cxl/pci: Remove hardirq handler for cxl_request_irq()Dan Williams1-6/+6
2023-09-29cxl/pci: Cleanup 'sanitize' to always pollDan Williams1-35/+25
2023-09-29cxl/pci: Remove unnecessary device reference management in sanitize workDan Williams1-5/+0
2023-09-15cxl/pci: Update commentIra Weiny1-1/+4
2023-09-11cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()Smita Koralahalli1-2/+1
2023-09-11cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registersSmita Koralahalli1-3/+3
2023-06-27cxl/pci: Use correct flag for sanitize pollingDavidlohr Bueso1-1/+1
2023-06-25Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-75/+46
2023-06-25Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams1-1/+25
2023-06-25Merge branch 'for-6.5/cxl-type-2' into for-6.5/cxlDan Williams1-93/+87
2023-06-25Merge branch 'for-6.5/cxl-fwupd' into for-6.5/cxlDan Williams1-0/+4
2023-06-25cxl: add a firmware update mechanism using the sysfs firmware loaderVishal Verma1-0/+4
2023-06-25cxl/mem: Wire up Sanitization supportDavidlohr Bueso1-0/+6
2023-06-25cxl/mbox: Add sanitization handling machineryDavidlohr Bueso1-3/+74
2023-06-25cxl/mbox: Allow for IRQ_NONE case in the isrDavidlohr Bueso1-2/+4
2023-06-25cxl/pci: Unconditionally unmask 256B Flit errorsDan Williams1-16/+2
2023-06-25cxl/mbox: Move mailbox related driver state to its own data structureDan Williams1-53/+61
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter1-9/+48
2023-06-25cxl/regs: Remove early capability checks in Component Register setupRobert Richter1-0/+2
2023-06-25cxl/pci: Refactor component register discovery for reuseTerry Bowman1-74/+5
2023-06-25cxl/core/regs: Add @dev to cxl_register_mapRobert Richter1-12/+11
2023-05-30cxl/pci: Find and register CXL PMU devicesJonathan Cameron1-1/+25
2023-05-23cxl/mbox: Add background cmd handling machineryDavidlohr Bueso1-0/+89
2023-05-23cxl/pci: Introduce cxl_request_irq()Davidlohr Bueso1-16/+23
2023-05-23cxl/pci: Allocate irq vectors earlier during probeDavidlohr Bueso1-4/+4
2023-05-18cxl: Move cxl_await_media_ready() to before capacity info retrievalDave Jiang1-0/+6
2023-04-23Merge branch 'for-6.4/cxl-poison' into for-6.4/cxlDan Williams1-0/+4
2023-04-23cxl/mbox: Initialize the poison stateAlison Schofield1-0/+4
2023-04-18cxl/pci: Use CDAT DOE mailbox created by PCI coreLukas Wunner1-49/+0
2023-02-14Merge branch 'for-6.3/cxl' into cxl/nextDan Williams1-8/+62
2023-02-14cxl: add RAS status unmasking for CXLDave Jiang1-0/+65
2023-02-14cxl: remove unnecessary calling of pci_enable_pcie_error_reporting()Dave Jiang1-11/+0
2023-01-30cxl/pci: Fix irq oneshot expectationsDan Williams1-1/+2
2023-01-30cxl/pci: Set the device timestampJonathan Cameron1-0/+4
2023-01-26cxl/mem: Wire up event interruptsDavidlohr Bueso1-10/+211
2023-01-26cxl/mem: Read, trace, and clear events on driver loadIra Weiny1-0/+33
2023-01-24cxl/pci: Show opcode in debug messages when sending a commandRobert Richter1-1/+1
2023-01-04cxl/pci: Move tracepoint definitions to drivers/cxl/core/Dan Williams1-111/+0
2022-12-06cxl/pci: Remove endian confusionDan Williams1-4/+3
2022-12-06cxl/pci: Add some type-safety to the AER trace pointsDan Williams1-2/+2
2022-12-05Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams1-40/+173
2022-12-05cxl/port: Add RCD endpoint port enumerationDan Williams1-0/+10
2022-12-03cxl/pci: Add callback to log AER correctable errorDave Jiang1-0/+20
2022-12-03cxl/pci: Add (hopeful) error handling supportDan Williams1-0/+137
2022-12-03cxl/pci: add tracepoint events for CXL RASDave Jiang1-0/+2
2022-12-03cxl/pci: Find and map the RAS Capability StructureDan Williams1-0/+8
2022-12-03cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams1-19/+6
2022-12-03cxl/pci: Kill cxl_map_regs()Dan Williams1-22/+1
2022-12-02cxl/pmem: Refactor nvdimm device registration, delete the workqueueDan Williams1-3/+0
2022-11-14cxl/doe: Request exclusive DOE accessIra Weiny1-0/+5
2022-07-19cxl/pci: Create PCI DOE mailbox's for memory devicesIra Weiny1-0/+44
2022-07-09cxl/mem: Convert partition-info to resourcesDan Williams1-1/+1
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams1-135/+0
2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreDan Williams1-44/+1
2022-05-19cxl/pci: Drop wait_for_valid() from cxl_await_media_ready()Dan Williams1-4/+0
2022-05-19cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()Dan Williams1-2/+2
2022-04-12cxl/pci: Make cxl_dvsec_ranges() failure not fatal to cxl_pciDan Williams1-9/+18
2022-04-12cxl/pci: Add debug for DVSEC range init failuresDan Williams1-3/+10
2022-04-12cxl/mbox: Use new return_code handlingDavidlohr Bueso1-1/+2
2022-04-12cxl/mbox: Improve handling of mbox_cmd hw return codesDavidlohr Bueso1-1/+1
2022-04-12cxl/pci: Use CXL_MBOX_SUCCESS to check against mbox_cmd return codeDavidlohr Bueso1-2/+2
2022-04-08cxl/pci: Drop shadowed variableDan Williams1-1/+0
2022-02-08cxl/pci: Emit device serial numberDan Williams1-0/+1
2022-02-08cxl/pci: Implement wait for media activeBen Widawsky1-1/+48
2022-02-08cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky1-0/+119
2022-02-08cxl/pci: Cache device DVSEC offsetBen Widawsky1-0/+6
2022-02-08cxl/pci: Store component register base in cxldsBen Widawsky1-0/+11
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams1-1/+1
2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky1-52/+0
2022-02-08cxl: Flesh out register namesBen Widawsky1-7/+7
2022-02-08cxl/pci: Defer mailbox status checks to command timeoutsDan Williams1-101/+33
2022-02-08cxl/pci: Implement Interface Ready TimeoutBen Widawsky1-0/+35
2021-11-15cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny1-60/+60
2021-10-29cxl/pci: Use pci core's DVSEC functionalityBen Widawsky1-24/+2
2021-10-29cxl/pci: Split cxl_pci_setup_regs()Ben Widawsky1-36/+37
2021-10-29cxl/pci: Add @base to cxl_register_mapDan Williams1-15/+16
2021-10-29cxl/pci: Make more use of cxl_register_mapBen Widawsky1-34/+25
2021-10-29cxl/pci: Remove pci request/release regionsBen Widawsky1-5/+0
2021-10-29cxl/pci: Fix NULL vs ERR_PTR confusionDan Williams1-1/+1
2021-10-29cxl/pci: Remove dev_dbg for unknown register blocksBen Widawsky1-3/+0
2021-09-21cxl/pci: Disambiguate cxl_pci further from cxl_memBen Widawsky1-33/+35
2021-09-21cxl/pci: Use module_pci_driverDan Williams1-22/+8
2021-09-21cxl/mbox: Move mailbox and other non-PCI specific infrastructure to the coreDan Williams1-922/+2
2021-09-21cxl/pci: Drop idr.hDan Williams1-1/+0
2021-09-21cxl/mbox: Introduce the mbox_send operationDan Williams1-55/+21
2021-09-21cxl/pci: Clean up cxl_mem_get_partition_info()Dan Williams1-24/+11
2021-09-21cxl/pci: Make 'struct cxl_mem' device type genericDan Williams1-40/+35
2021-09-07cxl/pci: Fix debug message in cxl_probe_regs()Li Qiang (Johnny Li)1-2/+2
2021-09-07cxl/pci: Fix lockdown levelDan Williams1-1/+1
2021-08-10cxl/mem: Adjust ram/pmem range to represent DPA rangesIra Weiny1-8/+6
2021-08-10cxl/mem: Account for partitionable space in ram/pmem rangesIra Weiny1-5/+91
2021-08-07cxl/pci: Store memory capacity valuesIra Weiny1-3/+33
2021-08-06cxl/pci: Simplify register setupBen Widawsky1-26/+12
2021-08-06cxl/pci: Ignore unknown register block typesBen Widawsky1-8/+12
2021-08-06cxl/core: Move memdev management to coreBen Widawsky1-227/+1
2021-08-06cxl/pci: Introduce cdevm_file_operationsDan Williams1-27/+38
2021-08-06cxl: Move cxl_core to new directoryBen Widawsky1-1/+1
2021-06-17cxl/pci: Rename CXL REGLOC IDBen Widawsky1-1/+1
2021-06-15cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams1-6/+17
2021-06-14cxl/pci: Add media provisioning required commandsBen Widawsky1-0/+19
2021-06-05cxl/pci: Add HDM decoder capabilitiesBen Widawsky1-0/+15
2021-06-05cxl/pci: Reserve individual register block regionsIra Weiny1-0/+2
2021-06-05cxl/pci: Map registers based on capabilitiesIra Weiny1-21/+90
2021-06-05cxl/pci: Reserve all device regions at onceIra Weiny1-7/+11
2021-06-05cxl/pci: Introduce cxl_decode_register_block()Ira Weiny1-8/+18
2021-05-26cxl/mem: Get rid of @cxlm.baseBen Widawsky1-13/+11
2021-05-26cxl/mem: Move register locator logic into reg setupBen Widawsky1-67/+68
2021-05-26cxl/mem: Split creation from mapping in probeBen Widawsky1-24/+40
2021-05-26cxl/mem: Use dev instead of pdev->devBen Widawsky1-1/+1
2021-05-26cxl/pci.c: Add a 'label_storage_size' attribute to the memdevVishal Verma1-0/+12
2021-05-26cxl: Rename mem to pciBen Widawsky1-0/+1524
generated by cgit 1.2.3-korg (git 2.43.0) at 2025-12-05 03:04:01 +0000