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| author | Jeremy Linton <lintonrjeremy@gmail.com> | 2019-05-16 12:10:17 -0500 |
|---|---|---|
| committer | Jeremy Linton <lintonrjeremy@gmail.com> | 2019-05-16 12:10:17 -0500 |
| commit | 8d124f0fc7c7acfec717935994bb877606d916ba (patch) | |
| tree | 6f62e87b237a8a4048cbd352525cdffe0822d728 /sys-utils/lscpu-arm.c | |
| parent | 4ac2ab97d18fc53b169d492168cc455d55887038 (diff) | |
| download | util-linux-8d124f0fc7c7acfec717935994bb877606d916ba.tar.gz | |
lscpu: Add additional aarch64 models
ARM has released docs for Cortex-A76, Neoverse-N1 and Neoverse-E1.
That means we know the midr partnums, so we can add them to the
human readable model name table.
Signed-off-by: Jeremy Linton <lintonrjeremy@gmail.com>
Diffstat (limited to 'sys-utils/lscpu-arm.c')
| -rw-r--r-- | sys-utils/lscpu-arm.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sys-utils/lscpu-arm.c b/sys-utils/lscpu-arm.c index 37b8f66f61..fd9ab3f470 100644 --- a/sys-utils/lscpu-arm.c +++ b/sys-utils/lscpu-arm.c @@ -70,9 +70,12 @@ static const struct id_part arm_part[] = { { 0xd08, "Cortex-A72" }, { 0xd09, "Cortex-A73" }, { 0xd0a, "Cortex-A75" }, + { 0xd0b, "Cortex-A76" }, + { 0xd0c, "Neoverse-N1" }, { 0xd13, "Cortex-R52" }, { 0xd20, "Cortex-M23" }, { 0xd21, "Cortex-M33" }, + { 0xd4a, "Neoverse-E1" }, { -1, "unknown" }, }; |