systemVerilog - How can I convert int unsigned to array logic?

Question

I have the following :

logic [15:0] tb_real_din, tb_image_din;
int unsigned counter;

   //write proc
   initial begin
      tb_last_dvalid = 1'b0;
      tb_we = 1'b0;
      #80ns;
      for (int i = 0 ; i <= 32; i++)
    begin
       counter = counter+1;
       tb_real = counter;
       tb_image = counter;
       if (i == 32)        
         tb_last_dvalid = 1'b1;
       #8ns;
       tb_we = 1'b1;
       #8ns;
       tb_we = 1'b0;
       tb_last_dvalid = 1'b0;      
    end     
   end // initial begin

I got the following error: Illegal reference to net "tb_real". How can I convert int unsigned to array logic?

Matthew · Accepted Answer · 2017-06-15 08:08:01Z

2

Your problem is nothing to do with converting between types. Your problem is probably because you have not declared tb_real. Anything undeclared in System-verilog defaults to being a 1-bit wire; a wire is a kind of net and it is illegal to assign to nets from initial, always or final blocks. Hence, your error message.

I say "probably" because you have not give an MCVE.

answered Jun 15, 2017 at 8:08

Matthew

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