No. You're going to need either a for loop or ten separate statements. The best way would be to write your own conversion function, but I guess you were really wanting to know whether the conversion could be done "in one go", so to speak.
There are two ways of converting types in VHDL. The first is a type conversion:
my_new_type_signal <= my_new_type(my_old_type_signal);
(or variable, obvs). This only works if my_new_type and my_old_type are closely related types. For example, integer and real are closely related, as are std_logic_vector and signed, but your two will not be.
The second way is to write a conversion function. Standard types (from the standard and numeric_std packages) have functions already written. Yours are not standard types, so you'll have to write your own.