vlog-7 error. failed to open design unit file in read mode

Question

i am trying to run an example design by IntelFPGA, using a tcl script provided by Intel. It reports 'error (vlog-7) failed to open unit file "blabla" in read mode. No such file or directory (errno = ENOENT). i can not find the error. Then i tried a modelsim project i used earlier, which used to work. I get the same error! What could be wrong?

At start of tb_run.tcl (run from commandline MODELSIM> VHDL 2008 do tb_run.tcl), this tb_run.tcl file is generated by quartus example

global env ;

# set QUARTUS_INSTALL_DIR "$env(QUARTUS_ROOTDIR)" => initially i thought
# there is something wrong with the rootdir, so i changed to the row 
# below:
set QUARTUS_INSTALL_DIR "C:/intelFPGA/18.0/quartus"
set SETUP_SCRIPTS ../setup_scripts
set tb_top_waveform msim_wave.do
set QSYS_SIMDIR "./../setup_scripts"

set TOP_LEVEL_NAME tb_top

source $SETUP_SCRIPTS/mentor/msim_setup.tcl

# Compile device library files

dev_com

================================================ => dev_com, this is line 29, here the error occurs, see below

modelsim reports:

Modelsim> VHDL 2008 do tb_run.tcl
# C:/intelFPGA/18.0/quartus
# ../setup_scripts
# msim_wave.do
# ./../setup_scripts
# tb_top
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with novopt option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Qsys base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# SILENCE                                           -- Set to true to suppress all informational and/or warning messages in the generated simulation script. 
# 
# FORCE_MODELSIM_AE_SELECTION                       -- Set to true to force to select Modelsim AE always.
# [exec] dev_com
# Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017
# Start time: 10:43:14 on Jun 25,2019
# vlog -reportprogress 300 C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v -work altera_ver 
# ** Error: (vlog-7) Failed to open design unit file "C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v" in read mode.
# No such file or directory. (errno = ENOENT)
# End time: 10:43:14 on Jun 25,2019, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# ** Error: C:/intelFPGA_pro/18.0/modelsim_ase/win32aloem/vlog failed.
# Error in macro ./tb_run.tcl line 29
# C:/intelFPGA_pro/18.0/modelsim_ase/win32aloem/vlog failed.
#     while executing
# "vlog C:/intelFPGA/18.0/quartus/eda/sim_lib/altera_primitives.v -work altera_ver"
#     ("eval" body line 1)
#     invoked from within
# "eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"             ..."
#     invoked from within
# "if [string is false -strict [modelsim_ae_select $FORCE_MODELSIM_AE_SELECTION]] {
#     eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_CO..."
#     ("eval" body line 5)
#     invoked from within
# "dev_com "

The question can be closed: i rebooted the system, and then the problem disappeared. — Pieter van Leeuwen
– Pieter van Leeuwen, Commented Jun 25, 2019 at 16:06

Alexey Tsibulnikov · Accepted Answer · 2020-11-09 11:56:04Z

3

Don't really know how you managed to solve this problem simply by rebooting. Here is what the problem most likely was about and how I solved it.

We have a statement about the problem: vlog-7 error. failed to open design unit file in read mode

I was too focused on the "read mode" and tried to figure out why is it forbidden to start declared operation. However the problem most likely is that you dont really have the actual file in the directory where warning occured.

Then I realised that I eventually changed the name of the folder and thus this file could not be read. Take a look that you didn't make any changes in pathing till your tcl, .do and project files.

answered Nov 9, 2020 at 11:56

Alexey Tsibulnikov

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3 Comments

Ralph Over a year ago

yep, my file didn't exist (wrong path name).

jakub-adamczewski Over a year ago

In my case I was adding file to project in wrong mode. In "Add file to project" window default option is "Reference from current location". Pick "Copy to project directory", it will save you a lot of time.

chami Over a year ago

The file was not located at the specified address for me. I had to search for the file name to find out its actual location. Then, I changed the address in the file. In my case, the file was called msim_setup.tcl

Alcohol without Smoking · Accepted Answer · 2023-09-23 01:27:22Z

0

My problem is that the project file is read-only, which makes it impossible to write a new path, so the file cannot be found.

The fast way to check this issue is copy the path to the folder windows, and press enter

answered Sep 23, 2023 at 1:27

Alcohol without Smoking

1

Comments

Georg · Accepted Answer · 2024-04-29 14:23:25Z

0

I had a problem like that too. In my Case the Project folder consisted of 2 words (eg. Hello World) and the second word was interpreted by Modelsim as a File. So the solution was to rename the folder to one word (eg. HelloWorld)

answered Apr 29, 2024 at 14:23

Georg

1

Comments

Bosworth Joe · Accepted Answer · 2025-04-23 15:39:29Z

0

I encountered the same problem. I solved it by just making sure that my folder does not have a space, and making sure to be able to open the path to check whether it's correct or not.

answered Apr 23 at 15:39

Bosworth Joe

212 bronze badges

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