Implementation of a SystemVerilog block in a Simulink simulation

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Tom Urkin 2021-3-11

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https://ww2.mathworks.cn/matlabcentral/answers/769472-implementation-of-a-systemverilog-block-in-a-simulink-simulation

回答： Kiran Kintali 2021-3-13

Hello all,

I have a synthesizable SV module that has been tested on an FPGA and as a part of a fabricated IC.

I would like to use this block in a Simulink simulation.

Would appriciate any help\thoughts since I could not find any relevant material online.

Thanks,

Tom

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Kiran Kintali 2021-3-13

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此回答的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/769472-implementation-of-a-systemverilog-block-in-a-simulink-simulation#answer_647133

https://www.mathworks.com/help/hdlverifier/matlab-cosimulation.html

Consider using cosimulation feature.

You can also integrate customer HDL Code in MATLAB using blackbox features in HDL Coder

https://www.mathworks.com/help/hdlcoder/ref/hdl.blackbox-system-object.html

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