Verilog binary addition

Question

Binary addition on A and B and outputs it along with proper carry bit. I'm not sure how to implement the carry bit

A and B are 4 bit inputs

C is 1 bit output that is used for the carry bit

module addop(C , O , A , B);
   input [3:0] A;
   input [3:0] B;
   output [3:0] O;
   output       C;

   assign C1 = A[0] + B[0];
   assign C2 = A[0] + B[1];
endmodule

Community · Accepted Answer · 2017-05-23 12:08:47Z

6

You may want to use a concatenation operator {} here.

module addop(C, O, A, B);
   input [3:0] A;
   input [3:0] B;
   output [3:0] O;
   output       C;

   assign {C, O} = A + B;
endmodule

Your synthesis tool will be responsible in converting them into logic gates.

See this question which is related to concatenation:

What do curly braces mean in Verilog?

edited May 23, 2017 at 12:08

CommunityBot

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answered Oct 23, 2015 at 2:04

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