How to tell in SystemVerilog that one of the module's outputs is directly connected to one of it's inputs?
Does it depend on the modeling level used? If yes, what is the right way for switch level?
module abc (input in1, in2, output out1, out2, out3);
// out3 needs to be directly connected to in1
// ...
endmodule
There are a number of ways to do this. But not all downstream tools like synthesis physical tools may support it.
This is the way to do it in SystemVerilog
module abc (input in1, in2, output out1, out2, out3);
// out3 needs to be directly connected to in1
// ...
alias out3 = in1;
endmodule
In Verilog
module abc (input .in1(sig), in2, output out1, out2, .out3(sig));
wire sig;
// out3 needs to be directly connected to in1
// ...
endmodule
alias, or assign, or connecting both ports to an internal net is better for some reason than the others for SystemVerilog (apart from current support by tools)?
alias. You lose strength propagation through an assign statement. If you are writing RTL, then an assign would be fine.
assign out3 = in1;?