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When a cache is first designed, is it randomly mapped with some memory addresses or does it is empty at the beginning and fills with memory/lower level cache data only after a load or store instruction from processor?

I have this question , since I have designed the RTL for L1 Cache. So should I leave it blank and wait for any processor to request a read/write or just fill it with some memory mapped data and then comprehend hit/miss accordingly?

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First designed? Do you mean first powered on? The normal way would be to start out with all the tags invalid (so it doesn't matter what's in the data arrays or anywhere else).

It's easy to imagine bugs if all the data in your cache was randomly initialized, so some lines would be valid, not-dirty, and have different contents than what's actually in RAM / ROM, so obviously you shouldn't do that. e.g. a hit in this out-of-sync L1 for the boot ROM code would be bad!

If any part of memory is initialized at power-on to known contents (like all-zeros), you could in theory init your cache tags and data so it's caching that memory.

If you init your cache as valid for anywhere that doesn't match what's in memory, you'd need to initialize it as dirty, which would trigger a writeback when the lines are evicted in favour of whatever the CPU actually needs, so that makes no sense.

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so that means that the cache is write allocated only after a processor requests a read/write Which also implies that there should always be a compulsory miss whatever be the address request be?
@ShankhadeepMukerji: yes. You have no information about what to pre-fetch, since no accesses have happened yet. If you want to hard-code the some default address that the CPU uses on reboot, you could save a couple cycles every reboot, but I'm pretty sure that's not worth spending any transistors on. Surely it's far easier to just make sure all the tags start out invalid? Any data has to get loaded from memory somehow, whether you prefetch it or whether it's a compulsory miss while running the initial instructions. Optimizing for reboots a few cycles faster seems insane.
Thanks @Peter Cordes

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