How to check if a signal does not change using Immediate Assertions in SystemVerilog Assertions

Question

I'm new to SystemVerilog Assertions and I know that I can check if a signal doesn't change between clock ticks using Concurrent Assertions:

assert property (@(posedge clk) enable == 0 |=> $stable(data));

But how would I do so continuously using Immediate Assertions? This is an example that I found online but I'm not sure if it's what I need and how it works:

assign not_a = !a;
always_comb begin : b1
    a1: assert (not_a != a);
    a2: assert #0 (not_a!= a); // Should pass once values have settled
end

dave_59 · Accepted Answer · 2017-06-16 15:07:08Z

1

What you are asking for does not make any sense. If it a signal never can change, then it must be a constant. With the example you show, a1 might fail - there is a race condition between a and not_a. a2 is deferred assertion - it takes care of the race and will never fail. But the problem with both these assertions is that if a changes at some time, a2 never fails and you may are may not see a failure with a1

answered Jun 16, 2017 at 15:07

dave_59

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5 Comments

Adam Billal Guergachi Over a year ago

Thank you for your comment. I think I didn't word my question properly, All I'm looking for is to use Immediate Assertions to check if a signal is stable, since I don't have a clock.

dave_59 Over a year ago

Without any reference, what is your definition of stable?

Adam Billal Guergachi Over a year ago

The signal does not change when the assertion is running.

dave_59 Over a year ago

So without any reference, when should the assertion start running, and when should it stop? My definition of stable means check for no change during some period or time window. You can't use the signal itself as a reference because it is indeed stable between its changes.

Adam Billal Guergachi Over a year ago

The signal A needs to stay the same when ever an other signal, B, is high. Sorry for all the confusion.

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