How to generate HDL code without the simulation

Question

I would like to generate HDL code without running the simulation. I managed to generate the code, but I had to run the simulation first. However, I would like to do it without this step. Is this possible, and how to do it?

Bogdan Vukobratovic · Accepted Answer · 2020-11-02 06:34:01Z

1

Yes, when a module is simulated using a HDL simulator (such as Verilator), running the simulation will automatically generate the HDL code for that purpose.

In order to directly instruct PyGears to generate HDL, you should use hdlgen() function which is available via:

from pygears.hdl import hdlgen

The function supports the following parameters:

top - Path to the module (within the design hierarchy) that should be generated. PyGears uses POSIX like paths, i.e. '/path/to/my/module`
lang - HDL language to use. SystemVerilog: 'sv' and Verilog: 'v' currently supported
outdir - Directory where to place the generated files
copy_files - When set to True it will also copy needed files from PyGears library to outdir. When set to False, you will have to make sure to include the PyGears libraries also when using the generated files.

answered Nov 2, 2020 at 6:34

Bogdan Vukobratovic

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