I was looking through some SystemVerilog code, and I came across this expression for testing if all the bits in a packed array were set.
logic [SIZE-1:0] array;
// Bool we are evaluating:
array == '1;
Can someone explain to me how this works? From what I have read, the '1 is treated as a signed integer, so perhaps it is sign extended to be all 1's? Just trying to make sense of this code snippet in my head.
Yes, the '1 notation is a convenient way to set all bits to 1, even for a comparison as in your code. Here is a small example to demonstrate:
module tb;
parameter SIZE = 3;
logic [SIZE-1:0] array;
initial begin
for (int i=0; i<8; i++) begin
array = i;
if (array == '1) begin
$display("true %b", array);
end else begin
$display("false %b", array);
end
end
end
endmodule
Prints:
false 000
false 001
false 010
false 011
false 100
false 101
false 110
true 111
IEEE Std 1800-2017, section 5.7.1 Integer literal constants, discusses this:
An unsized single-bit value can be specified by preceding the single-bit value with an apostrophe ( ' ), but without the base specifier. All bits of the unsized value shall be set to the value of the specified bit.
'0, '1, 'x and 'z are fill literals(See section 5.7.1 Integer literal constants in the IEEE 1800-2017 SystemVerilog LRM). Using the rules for expression bit widths (section 11.6.1), these literals are filled to the determined width with all 0,1,x, or z's. In this case, to the width of array. In a self-determined context, i.e. stand-alone literal, they would just be a single digit.
