Cache line sizes for AMD Zen 3 Architecture

Question

I wanted to see if I am correctly interpreting the attached diagram.

It shows the AMD Zen 3's cache lines.
OC Fetch is Opcode Cache,
IC Fetch is Instruction Cache.

I am just unable to make sense of the way IC fetch and OC fetch are depicted alongside the cache lines.

AMD Zen 3 Cache lines...

I was confused by how IC and OC fetch widths were shown, regarding how they should be interpreted... I have taken an introductory course in CPU architectures and microarchitectures, so reading the modern CPU designs is a first for me. — Kush Jenamani
– Kush Jenamani, Commented May 29 at 3:58

Peter Cordes · Accepted Answer · 2025-05-27 16:02:35Z

1

Other than the uop cache, all lines are 64 bytes in all levels, in all x86 for the last couple decades from all vendors. (Some hardware prefetch likes to complete 128-byte-aligned pairs of cache lines, e.g. in Intel's L2, so you can get some false-sharing interference between separate cache lines, but not as bad as same-line.)

Probably the OC-fetch spanning two L1i lines is showing that a single uop-cache entry can contain uops that span a boundary between L1i lines. (Intel Sandybridge couldn't do this, and AFAIK that's still the case in current Intel, that all uops in 1 way of the cache have to start in the same 32-byte chunk of machine code.)

The diagram is showing that fetch from L1i (to feed the legacy decoders) is 32 bytes wide, and can be misaligned by 16. But not arbitrary misalignments.

answered May 27 at 16:02

Peter Cordes

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