Implicit Build Rules: GNU Make Multiple Makefiles Multiple Directories

Question

I have the following directory structure:

.
..
./Graphic/
./Graphic/SymbolXLib

There are several other directories in this project but I won't list them for simplicities sake.I want a main makefile that drives the build of other Makefiles stored in their own directories. There are several project comming together, so I can't just move source around.

The main makefile is defined as:

[mehoggan@hogganz400 Core]$ cat ./Makefile 
CORE_LIBS_DIR = libs
OBJS_DIR = obj/symb_obj
include ./Graphic/SymbolXLib/Makefile

The Graphic makefile is defined as:

#
# make BUILD_MODE={release|debug} OS_ARCH={32|64}
# 
# default is 32-bit release build
#
BUILD_MODE = release

OS_ARCH = 64

OBJS_DIR = $(BUILD_MODE)$(OS_ARCH)

SRC = \
  ./Graphic/SymbolXLib/CartoCursor.cpp \
  ...
  ./Graphic/SymbolXLib/TextureConversion.cpp \
  $(NULL)

CC = gcc -fPIC
OBJS = $(SRC:%.cpp=$(OBJS_DIR)/%.o)

COPTS = -m$(OS_ARCH) -O2

CDEFS = -DLINUXx86 \
        -I../../../SharedArcGIS/Include/GraphicsPipeline/Display/SymbolX/SymbolXLib \
        -I../../../SharedArcGIS/Include/System/Geometry/GeometryXLib \
        -I../../../ArcSDE/pe/include \
        -I../../../ArcSDE/shape/include

CFLAGS = $(COPTS) $(CDEFS) $(CINCS)
TARGET = libSymbolXLib.a

all : $(OBJS_DIR) $(OBJS_DIR)/$(TARGET)

$(OBJS_DIR) : 
        mkdir -p $(OBJS_DIR) 

$(OBJS_DIR)/$(TARGET) : $(OBJS)
        ar qc $@ $^

$(OBJS_DIR)/%.o : %.cpp
        $(CC) -c $(CFLAGS) -o $@ $<

The response at the previous post (Previous Post) helped only if I moved alot of things around. I can't do this. So the question still remains, how do I get make to recognize the implicit build in a subdirectory from the main Makefile?

The error I am getting is

make: *** No rule to make target `release64/./Graphic/SymbolXLib/CartoCursor.o', needed by `release64/libSymbolXLib.a'.  Stop.

sarnold · Accepted Answer · 2011-12-30 01:34:29Z

3

I have to think you'd have far better success if you avoided include and instead use recursive make. In the top-level Makefile, something like:

graphic:
    $(MAKE) -C Graphic

And the Makefile in Graphic/Makefile can have its sub-projects:

symbolxlib:
    $(MAKE) -C SymbolXLib

and so on. You might need to add each of the targets to a default target or something similar to hang them all together on a single execution. You could give each of these targets an actual dependency (they should be .PHONY: if they don't have a dependency...) to rebuild them only when necessary or when commanded to by an upper-level target that touch(1)es "command files".

Alternatively, this paper recommends a different approach to avoid recursive make, but I've not yet read it -- and have found recursive make works well enough in projects I've been a part of that I don't mind recommending it.

answered Dec 30, 2011 at 1:34

sarnold

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1 Comment

Aleksandr Blekh Over a year ago

Hello! May I ask your opinion on this related question: stackoverflow.com/questions/24573413/…? (Please also see my linked questions in panel on the right.) Thank you!

Francis Upton IV · Accepted Answer · 2011-12-30 01:28:22Z

2

Does this gnumake documentation help you?

answered Dec 30, 2011 at 1:28

Francis Upton IV

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