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About the SystemVerilog category
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0
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1187
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January 1, 2023
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Query on generating rand 2D array with sum of set bits equal to specific value and bits must be connected to each other
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2
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18
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November 30, 2025
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Adding and deleting elements of dynamic type at same time
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2
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23
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November 29, 2025
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Time does not strictly flow forward
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1
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17
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November 28, 2025
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Force a bunch of internal signals when there another particular signal goes high
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2
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21
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November 27, 2025
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SVA sequence re-triggers on multiple $fell events – rise_t not updating
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1
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28
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November 19, 2025
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Continuous assignment between two inout
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3
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29
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November 19, 2025
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Redefine a SV interface port direction in a modport
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2
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65
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November 19, 2025
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Resume simulation when any 2 threads out of 3 get completed within fork-join_any
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9
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4159
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November 12, 2025
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Verifying synchronours fifo
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3
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58
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November 11, 2025
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Question regarding followed by operator in SVA (#-# and #=#
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0
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40
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November 11, 2025
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System verilog constraint help
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2
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67
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November 11, 2025
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Need help understanding formal verification of asynchronous FIFO
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0
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42
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November 3, 2025
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Chained Implications in SVA
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0
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40
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November 3, 2025
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Why only ##1 (single delay operator) used in the case of multiple clock sequences?
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2
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659
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November 3, 2025
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Once a certain sequence occurs that another seq shouldn't occur till simulation ends
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7
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617
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November 2, 2025
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restricting sequence as long as one variable is asserted
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4
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60
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November 2, 2025
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Default value of enumarated varaible is first value of enum
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4
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53
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November 1, 2025
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difference b/w nexttime and ##1
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1
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43
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October 31, 2025
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Paper: Understanding SVA Degeneracy
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9
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564
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October 29, 2025
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SVA with multiple Implication operators
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0
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42
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October 29, 2025
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Function inside constraint
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1
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63
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October 28, 2025
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is $fell(sig_a) true when sig_a from x to 0?
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1
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43
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October 27, 2025
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Question regarding latch behaviour
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1
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52
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October 27, 2025
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Understanding the throughout SVA
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11
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1074
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October 20, 2025
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SV assertion related to req and grant
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2
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72
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October 18, 2025
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Is there an alternative to sum() Constraint
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5
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1860
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October 19, 2025
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Difference between -> and => in assertions
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5
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163
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October 19, 2025
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QuestaSim not loading design after restart -f
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2
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34
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October 17, 2025
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What operators constitute a multi-threaded sequence
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1
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61
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October 16, 2025
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