In reply to dave_59:
I have seen the examples and it does seem very trivial. They are both compiled into the same work lib, but the vlog -L flag gets around this.
So i am still a little puzzled that i still have errors here.
Just to confirm my vcom and vlog commands and the resultant error.
vcom -32 -2002 -l design.log -work design +cover=bcesft -novopt -mixedsvvh -f /home/user7/design.f
vlog -32 -work work -timescale 1ns/1ps -writetoplevels questa.tops +incdir+/APPS/questasim/10.3a/questasim/verilog_src/uvm-1.1d/src -mfcu -incr +acc=varg -L design -f /home/user7/testbench.f
I have imported the vhdl package into my interface, but i am still unable to use the VHDL record types. The vlog compilation error is still related to visibility.
** Error: ** while parsing file included at …/tb/top/registerHW_if/registerHW_pkg.sv(19)
** at …/tb/top/registerHW_if/registerHW_if.sv(49): (vlog-2143) Unable to find ‘register_outputs’ in scope registerHW_if.
** Error: ** while parsing file included at …/tb/top/registerHW_if/registerHW_pkg.sv(19)
** at …/tb/top/registerHW_if/registerHW_if.sv(50): (vlog-2143) Unable to find ‘register_inputs’ in scope registerHW_if.