Understanding combinational feedback loops

Think about what is combinatorial logic?
Logic gates where the output is defined entirely by the input, there is no state.

Imagine b = XOR of a and b.

a changes to 1 output changes to 1 loops back xor is now 0, feedback means xor is now 1 etc.

This is an uncontrolled oscillation which will only stop when the input a is set 0 and it will stop in an undetermined state.

The example above should be able to code as: but any combinatorial logic which reuses an output is a loop.

input a;
reg b;

always @* begin
  b = b ^ a; 
end

or

input a;
wire b;
assign b = b ^ a;

Combinatorial feedback loops are usually undesirable because the output will oscillate and the output is unpredictable. However, sometimes that's exactly what you want -- a hardware random number generator (RNG). Altera has released some example verilog code that does exactly that. See 14–2 in their Advanced Synthesis Cookbook.

Here's one of their examples, found here, under random/ring_counter.v:

module ring_counter (clk,rst,out);

parameter DELAY = 100;

input clk,rst;
output [15:0] out;

wire [DELAY-1:0] delay_line /* synthesis keep */;

reg [15:0] cntr;
reg sync0;
reg wobble;

// unstable ring oscillator
genvar i;
generate
for (i=1; i<DELAY; i=i+1)
  begin : del
    assign delay_line [i] = delay_line[i-1];
  end
endgenerate
assign delay_line [0] = !delay_line [DELAY-1];

// sync it over to the input clock
always @(posedge clk) begin
  sync0 <= delay_line[0];
  wobble <= sync0;
end

// count when the wobbly oscillator is high
always @(posedge clk or posedge rst) begin
  if (rst) cntr <= 0;
  else if (wobble) cntr <= cntr + 1;
end

assign out = cntr;

endmodule