Questions tagged [system-verilog]
In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.
549 questions
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Use of new constructor in extended classes from uvm base classes
Code link: [https://edaplayground.com/x/9cte]
For the below code
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Ral model - predictor and adaptor, correct chronological paths
let say I have a simple DUT that contain 1 register that can be written or read.
this DUT works in a way that when accessing this register (by request), it would return a response.
is this the correct ...
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134
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JK flip flop behavior on startup in Verilog
I've tried to implement a JK flip flop in Verilog, but while testing, I found that whatever inputs of j and k I give on startup, until I reset the flip flop (j=0, k=1), the outputs will not be seen ...
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Why is the waveform not matching? (2 clock delay in FSM code)
Context : I have been tasked with testing a HC-04 Ultrasonic sensor with Verilog, and below is the Verilog code, the testbench and the waveform that I am getting,
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111
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Different outputs for RTL and gate level netlist simulations for a latch used in clock gating
I am trying to implement clock gating logic manually using a latch and an AND gate as shown in the figure.
The latch has an enable (en) and a done signal which are ...
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What to do when a Verilog state machine simulation doesn't reflect the signals?
I'm working on a Verilog project using ModelSim, and I've created a testbench to simulate the behavior of a module called Elevator_FSM, which models an elevator's operation.
My goal is to assign ...
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124
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Analyzing unexpected output from Verilog bit unpacking and reassembly logic
I'm working on a Verilog task that rearranges bits from a 312-bit word into a new 312-bit format using 8-bit temporary storage (temp[39]). Below is a simplified ...
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How blocking assignment affect non-blocking assignment in Verilog?
module t;
reg a;
initial a <= #4 0;
initial a <= #4 1;
initial $monitor ($time,,"a = %b", a);
endmodule
Output of above Verilog code is:
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438
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Why is Vivado connecting this reset to the CE pin when the R pin is available?
Vivado is connecting up the reset signal through a LUT to the CE pin of the FDRE, even though the R pin is available. This is a 2k signal, and it's using up 2k LUTs to do this, unnecessarily. Any ...
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Vivado Simulation Bug for 4 bit asynchronous ripple counter
I am currently learning Verilog and tried to build an asynchronous counter using T flip flops.
But, during the simulation, my most significant three bits become one without any clock signal from the ...
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123
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SystemVerilog's $fdisplay/$fopen don't create a file
I am trying to save the results of simulation to a file from a testbench. Here is the problematic snippet:
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65
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Clocking block skew in interface modport
For the code: EDA Playground
In the interface code:
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114
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How can I make sure the signal is not X when accessed?
I just found a bug in hardware that wasted hours of my time, and I never thought about it.
I have something like that:
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144
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Bad handle reference while calling a task in SystemVerilog
I am trying to create the basic testbench for a simple single port memory but getting the following error:
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How to use a macro as a parameter?
I want to handle 2 scenarios in a module. The difference is very minimal, few lines at worst.
The scenario depends on the instantiation and I would like to avoid having to have 2 separate files for it....
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Temporal parallelism
I am trying to implement a temporally parallel hardware design.
The idea is to run multiple quater-rounds in a pipline-like fashion.
When I run simulation, I get back this waveform:
Why is the ...
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Fixed-point number adder simulation result is unexpected
I wrote a Verilog code for fpadder, and when I simulate it with the ModelSim software, it generates a series of incorrect numbers with the provided test bench. So far, I have realized that the ...
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Why does ROM use nonblocking assignments?
I have a SystemVerilog module representing a 4-word x 3-bit ROM. It's from a textbook (Harris & Harris Digital Design and Computer Architecture), so I'm sure this isn't a typo. I understand that ...
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ModelSim: Non-Synthesizable Verilog Reference
Where would I find a good reference (or even cheat sheet) on the non-synthesizable functions/syntax/commands that can be used in Verilog with ModelSim?
In other words, where would I find a complete ...
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122
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FSM state counter Verilog simulation is not working as expected
I have written an FSM Verilog code. For making transition from state S3 to S2 of the FSM , we wait for the signal b or 2 clock cycles, whichever happens first. Here are the design and ...
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Registers don't update in Verilog 4-bit processor implementation using iverilog
Link to old question on Designing a 64-bit RISC processor in Verilog
Fixed code with no compiler errors being thrown:
cpu.v
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Implementing a Cube Root Calculator in Verilog
Update : I never got Newton-Raphson to work. I would suggest trying this with either Binary Search or a digit-by-digit approximation if you are facing similar issues.
I am trying to implement a cube ...
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2
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Cast Verilog 16-bit expressions to 8 bits
How do I cast from 16 bits to 8 bits?
...
output [ 7:0] audioData );
bit [15:0] audioSum;
// Get the 8-bit output
assign audioData = (audioSum >> 1);
I ...
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158
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Verilog always block not clocking
I have a 28Mhz clock which toggles a slowClk every 14 cycles:
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158
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SystemVerilog assertions for formal verification
I am learning basic SV assertions for formal verification. For practicing the assertions, I am given some statements and asked to write assertions for them. These are just statements demanding certain ...
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98
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Confusion regarding the $past() function in SystemVerilog simulation
For the following code on simulation, I am getting stable_4_clk[0]=1 at 30 ns and 0 at 40 ns. I thought it would be vice-versa. What is the reason for ...
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2
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423
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Verilog parsing ambiguity
I am struggling with a couple slightly strange conflicting conventions in Verilog. I have written my own parser, but I am uncertain how to resolve a few things. Looking at the Verilog Spec, I am still ...
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107
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Unexpected behaviour of ternary operator in SystemVerilog
I was running the following code and found out that the out1 and out2 are different if I pass in1 or in2 as negative.
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231
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system verilog code error
I developed this code for a Graph convolutional network (GCN) module in system verilog:
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How to solve "Redeclaration of port 'logic' is not allowed" error while synthesizing SystemVerilog code in dc shell?
I am very new to SystemVerilog and am still learning the syntax. I wrote this code for a graph convolutional network (GCN) module.
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Copying dynamic array does not share same memory
I am trying to understand how the copying of the dynamic arrays work in SystemVerilog.
Here is a small code snippet I was trying:
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94
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Couple a signal onto another one SystemVerilog
I have a circuit that has 2 ports, A and B, connected through a switch. I want to couple only the signal that's on A port to another port C. I don't want B port to couple on C. This is what I have:
<...
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2
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573
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Passing SystemVerilog function arguments
I am finding it hard to understand how handle passing in function arguments works. I have written 3 codes. The last one is giving a bad handle error.
First I would like to know if I am right in ...
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514
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Usage of edge-triggering constructs in Verilog
I want to know if following code is syntactically, synthesiszably correct? Is it a recommended practice, if not, why? Assuming that count is a register which is ...
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In SystemVerilog, can two always_ff blocks be executed in parallel?
Some articles say that if I want to achieve different functions / tasks, it's better to separate the sensitivity list into multiple blocks. So, I'm wondering if I can really do this?
For example, ...
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Why does active-region process execute during program's #0 in Questa?
Consider the following snippet.
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109
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How should deferred assertions behave in a combinatorial testbench?
Consider the following SystemVerilog snippet.
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What to watch out for in combinatorial logic in reset value?
I have a register that I want to update using two different mechanisms
Shifting left, triggered by signal a
Updating the whole value, triggered by signal ...
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3
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760
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SystemVerilog threads execution order
I am trying to start few threads in SystemVerilog, as can be seen in the code below:
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529
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Why can't I set max delay between pins for my FPGA?
I'm a software engineer just starting to play with FPGAs (Currently,Nexys A7 100T). I'm having a heck of a time getting the constraints to do what I want, and I can't seem to find the answers online.
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Verilog: Comparing signed value vs. unsigned value yields unexpected result
In Verilog, I want to compare signed and unsigned values. The following code (val > valS) gave me unexpected result. In the code below, unsigned variable (val) ...
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2
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203
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A curious case of combinational logic
I am running circles around the following scenario and have no idea of where the solution will be. The task is to implement the following gray to binary converter in SystemVerilog:
I adapted a ...
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71
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Can generated events get placed before events already in the event queue in SystemVerilog?
I tried to consult the Verilog LRM but wasn't successful; some of the reason is because I don't really know the correct terminology. This question is related to this one here, but I never got an ...
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814
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Synthesizable system verilog code to find least number in an array
I have tried a few ways using for loops to find the least number in array, but having a hard time in updating the pointer whenever a new least value is encountered. I am following the below textbook ...
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How can I reduce the amount of resources I'm using in this system verilog design
I want to implement a design that follow a paper written by a researcher the part, this lead us to this picture that resume what the code I have so far is supposed to do:
As you can se the goal is to ...
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Creating entity/module containing IP from different vendors
In FPGA design often we need to instantiate vendor specific IP. This could be simple things like Block RAM and DSP. It could be more complex things like FPU IP. The 3rd party IP is directly ...
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720
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Using a parameter as a macro in system verilog code
Assume that I have below module definition with a parameter N:
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