Unexpected behaviour of ternary operator in SystemVerilog

I was running the following code and found out that the out1 and out2 are different if I pass in1 or in2 as negative.

module multiplexor
#(
    parameter WIDTH1 = 4,
    parameter WIDTH2 = 8
)
(
    input  logic signed [WIDTH1 - 1 : 0] in1  ,
    input  logic signed [WIDTH2 - 1 : 0] in2  ,
    input  logic sel ,
    output logic signed [WIDTH2 : 0] out1  ,
    output logic signed [WIDTH2 : 0] out2 
);

    logic signed [WIDTH2 : 0] w_sum_in;
    
    assign w_sum_in = $signed(in1) + in2;
    assign out1 = sel ? w_sum_in : {(WIDTH2+1){1'b0}};
    assign out2 = sel ? ($signed(in1) + in2) : {(WIDTH2+1){1'b0}};

endmodule

The input-output values are as follows while I was testing it:

xcelium> run
---------------------
in1 =  15 in2 =   89
out1 =  104
out2 =  104
---------------------
in1 =  10 in2 =    0
out1 =   10
out2 =   10
---------------------
in1 =   4 in2 =  -15
out1 =  -11
out2 =  245
---------------------
in1 =   0 in2 =  -15
out1 =  -15
out2 =  241
--------------------

I feel both the outputs should be same, but instead of doing the signed extension, it's padding 0 at the MSB and making the whole output positive.

Is there any rule to be followed while using ternary operator or solution to this problem?