Enabling sampling of coverage group in SystemVerilog

Question

I am trying to run with functional coverage on my code, but I am getting a warning stating:

Sampling of covergroup type "LED_PANEL::CVG" (./design.sv:24), referred in 
the statement is not enabled. As a result, coverage methods get_coverage(), 
get_inst_coverage(), get_hitcount(), and get_inst_hitcount() will return 0 coverage.
 0.000000 %

I am not getting coverage printed in the log either. How do I enable coverage?

Here is the coverage group I have created:

  covergroup CVG;
    LED11: coverpoint PANEL[0][1];
    LED12: coverpoint PANEL[0][2];
    LED13: coverpoint PANEL[0][3];
    LED14: coverpoint PANEL[0][0];
    LED21: coverpoint PANEL[1][1];
    LED22: coverpoint PANEL[1][2];
    LED23: coverpoint PANEL[1][3];
    LED24: coverpoint PANEL[1][0];
  endgroup: CVG

Here's the link to the code: https://edaplayground.com/x/KUv3

This is a tool specific setup issue for EDAPlayground. Selecting other tools works fine. — dave_59
– dave_59, Commented Jun 27, 2023 at 2:53

toolic · Accepted Answer · 2023-06-26 17:32:58Z

2

The Cadence simulator requires you to enable functional coverage when you run the simulation. I added the required settings, and the coverage results are shown:

EDA Playground

  Coverage: 100.000000 %

I added -coverage all to the "Compile options"

answered Jun 26, 2023 at 17:32

toolic

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