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Questions tagged [edge-detection]

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I'm using the TI TPL5111 in one-shot mode to enable an LDO for about 30Min. My mission is to start counting 30Min when I detect falling of signal EXT_IND. According to the TPL5111 datasheet, the ...
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I'm working on creating a logic circuit that can detect which of the signals B and C have the first rising edge after a falling edge of signal A. The output should be low if B is first and high if C ...
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I want to know if following code is syntactically, synthesiszably correct? Is it a recommended practice, if not, why? Assuming that count is a register which is ...
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I have a mechanical assembly with 24 switches, limit switches, selectors, etc. and this assembly along with a box filled with electronics will go and suffer a very long shock and vibration test. I ...
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I have a simple rising edge detector on the top and a falling edge detector at the bottom. The switches represent low-side switched sensor. In fact, I only have one sensor. How do I use one sensor ...
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I'm practicing Verilog using the HDLBits website, and I am trying to solve this problem where I have been given a 32-bit wide input signal and I have to detect whenever a ...
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I want to build a circuit that counts the on and off of a reed switch in a CD4040 binary counter. I wired the circuit below in a breadboard. This has a debounced switch connected to a 74HC86 that when ...
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I tried to simulate (before building it) a double edge detector circuit that I found in this post. When I simulated it, I got a decent pulse when I closed the switch but when I opened it, I got a ...
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TI manufacturers two near-identical drivers for matrixed LEDs, LP5890 and TLC6983. I was only able to determine the following ...
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I have a requirement to generate a 4 sec pulse when a switch is closed and another pulse when the switch is open with minimal (<10uA) to zero power consumption when the pulses are not being ...
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Given 1 hall sensor. It can be in: State 1: Static 0 (no oscillations) State 2: Static 1 (no oscillations) State 3: Edging 0/1 at different frequencies Given also an MCU which counts the positive ...
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Hi I'm trying to come up with a name for when a change in input is detected and an interrupt is issued due to that. So I want to "trap" a change in an input, but a trap already means a ...
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I am designing a pulse circuit which I will be feeding to a comparator. I am using a combination of resistor capacitor and diode for generating positive edge triggered pulse as shown in the below ...
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I am developing a driver for an SPI temperature sensor, and having some trouble with poor quality edges near the end of packet on the data lines. While I am not experiencing any data loss, I am ...
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I have a falling edge detector built based on a D flip-flop as shown in the following figure: Components: 74hc74, 74ls04n, 74hc08 A sample output is shown below (I ...
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on the raspberry PI 3 computer IO boards datasheet it has on page 10 (first sheet) is has the option to connect jumper 13-14 to wake up the computer module by connecting global_en to run_pg run_pg is ...
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I'm currently learning about flip-flops, and I'm curious about the different ways in which the clock signal is handled. So far I've come across 3 different techniques: AND-ing the clock signal with ...
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I keep coming back here searching for an RC-based negative edge detector for TTL levels, that generates a negative pulse on a falling edge. The only place I find this solution is a certain spot in a ...
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Continuing with my edge triggered ramp generator and its simulation, thanks to all your help I have the LTspice simulation set up that I can see a theoretical circuit work that uses the rising edge of ...
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I have an application where a rotating plastic wheel has ferromagnetic inserts on the circumference of the plastic wheel (they don't stick out). Shown below in the picture is the plastic wheel (black)...
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I am getting a little desperate here. I thought I could replace a single 4-bit D-flip-flop register 74LS173 with the 4 x 4-bit register file 74LS170 or 74LS670. But the problem is that it is a level ...
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I have 74LS170s and 74LS670 register files which have the trouble that they are not edge triggered but like SRAM accept data for the entire duration of the write gate being low. So, I have the ...
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