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I'm practicing Verilog using the HDLBits website, and I am trying to solve this problem where I have been given a 32-bit wide input signal and I have to detect whenever a 1 to 0 transition occurs and set the corresponding output bit high until I receive a reset signal. If both the transition and the reset occur simultaneously, the reset takes precedence. The reset is a synchronous reset.

A sample waveform is attached below:

Waveform

My attempt at this problem was to find the AND of the input at the previous clock cycle and the negative of the input in the new clock cycle to set the bit where the 1 to 0 transition occurred. My logic:

Input (previous clock cycle): 10011001

Input (next clock cycle): 01001010

Negative of that input: 10110101

AND of old input and new input: 10010001

Verilog code:

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0]in_prev;
    always @(posedge clk) begin
        in_prev <= in;
        if(reset)
            out <= 32'b0;
        else
            out <= in_prev & ~in;
    end
endmodule

However, the console shows me that my code is wrong and there are mismatches in the waveform. Can anyone tell me why this is happening?

Mismatch waveforms:

Mismatch1 Mismatch2

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  • 2
    \$\begingroup\$ You're not holding the output bits until the reset occurs. You're simply doing a fresh edge detection on every clock cycle. \$\endgroup\$ Commented Sep 25, 2023 at 3:31

2 Answers 2

Reset to default
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You should set an output bit only if a negative edge was seen on the input bit. I find in clearer to create a dedicated combinational logic signal to show the negative edge detection (refer to signal ne in the code below). I also find it easier to understand if I use a for loop to check each input bit when setting the output:

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);

    reg [31:0] in_prev;

    always @(posedge clk) begin
        in_prev <= in;
    end

    wire [31:0] ne = (~in) & in_prev;

    always @(posedge clk) begin
        if (reset) begin
            out <= 0;
        end else begin
            for (int i=0; i<32; i++) begin
                if (ne[i]) out[i] <= 1;
            end
        end
    end
endmodule

This code passes on HDLBits.

Here is how your code behaves (in a pseudocode example):

On the positive edge of the clock, if reset is low:

 if (in=0 and in_prev=1) then set out = 1
 otherwise, set out = 0

It is the otherwise clause that causes the problem in your code.

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  • \$\begingroup\$ I changed my code based on the suggestion made by @dave-tweed, I set the else condition as out <= out | (in_prev & ~in) so that the output bits are being held until the reset occurs and this passed on HDLbits. Is this a good method to go about implementing such a logic or do I have to use a for loop for this purpose just for the sake of best practice? \$\endgroup\$ Commented Sep 26, 2023 at 2:21
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    \$\begingroup\$ @Socks: In this case, it is a matter of preference. Use whatever coding style is easier for you to understand. \$\endgroup\$ Commented Sep 26, 2023 at 10:12
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//Positive Edge Detection

module pedge_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0]store = 8'd0;
    always @(posedge clk) begin
       store <= in; 
    end
    always @(posedge clk)begin
        pedge <= in & (~store);
    end
    
endmodule
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  • \$\begingroup\$ Please use the code markup features to format your answer. \$\endgroup\$ Commented Apr 8, 2024 at 22:31
  • 1
    \$\begingroup\$ Your answer could be improved with additional supporting information. Please edit to add further details, such as citations or documentation, so that others can confirm that your answer is correct. You can find more information on how to write good answers in the help center. \$\endgroup\$ Commented Apr 9, 2024 at 4:41

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