I want to be able to manual address a 4gb ddr4 memory stick. looking at the datasheet for ddr 4 there are only address pins from A0 to A17 which is 18 bits, 2^18 = 262, 144 address spaces. So how does it address 4gb? It would need 32 bits right?
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1\$\begingroup\$ Welcome to the site. Please see that this cannot be an on-line technical encyclopedia, copied out to you on demand. People will help you take the next step if your question shows you've done as much as you possibly could on your own - which yours doesn't, I'm afraid. This is basic information that any text on DRAM will explain. I recommend that you search the internet for 'SDRAM addressing'. Voting to close for those reasons but a warm welcome to the site and hope to help on future visits. \$\endgroup\$TonyM– TonyM2019-08-23 19:54:51 +00:00Commented Aug 23, 2019 at 19:54
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2 Answers
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The addressing is not straight forward as in 8080 interface. You can study in detail.
- Bank Group
- Bank
- Row
- Column
There are many other control signals such as RAS and CAS.
https://www.systemverilog.io/ddr4-basics
Please go through the link above several times. Please ask more questions if you find something doubtful.
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\$\begingroup\$ The DDR4 Basics article on systemverilog.io is a fantastic overview! Thanks for the tip. \$\endgroup\$natevw– natevw2021-09-03 18:13:36 +00:00Commented Sep 3, 2021 at 18:13
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These address pins are used in a multiplexed fashion for row and column addresses. Extremely simplified, it means that accessing 4 GB (which needs 32 address bits) only 16 address bits are sent at a time in two parts. In reality it is slightly more complicated as there are X rows and Y columns and Z banks in a single chip and there are multiple chips per memory module which all add up to the total module size.
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\$\begingroup\$ So it takes twice as long to address a word of memory? That seems inefficient. \$\endgroup\$person– person2019-08-23 19:57:14 +00:00Commented Aug 23, 2019 at 19:57
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\$\begingroup\$ No, it takes much longer. When first opening a row for access, it also takes 15-20 clock cycles of CAS latency before first data bit can be read. But as multiple bits can be transferred one after another in a burst, the throughput compensates for the delays. That's why caches exist. \$\endgroup\$Justme– Justme2019-08-23 20:15:58 +00:00Commented Aug 23, 2019 at 20:15
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\$\begingroup\$ @person, the interface clock is much faster than the DRAM array access speed. But look on the internet, this is all there. All written out in great detail. \$\endgroup\$TonyM– TonyM2019-08-23 20:21:09 +00:00Commented Aug 23, 2019 at 20:21