Resolving an issue with syntax in SystemVerilog

I am trying to build a 4:1 multiplexer using 2:1 multiplexers that I've built. I am getting a few errors whenever I try typing the command:

vsim mux4_test

Array connection type 'reg$[1:0]' is incompatible with 'wire[1:0]' for port (sel): can't mix packed and unpacked types.
** Error (suppressible): (vsim-3053) mux2.sv(19): Illegal output or inout port connection for port 'Z'.
#    Time: 0 ns  Iteration: 0  Instance: /mux4_test/m4a/mux2a/g6 File: NOT.sv
# ** Warning: (vsim-3015) mux2.sv(19): [PCDPC] - Port size (1) does not match connection size (32) for port 'Z'. The port definition is at: NOT.sv(3).
#    Time: 0 ns  Iteration: 0  Instance: /mux4_test/m4a/mux2a/g6 File: NOT.sv
# ** Error (suppressible): (vsim-3053) mux2.sv(19): Illegal output or inout port connection for port 'Z'.
#    Time: 0 ns  Iteration: 0  Instance: /mux4_test/m4a/mux2b/g6 File: NOT.sv
# ** Warning: (vsim-3015) mux2.sv(19): [PCDPC] - Port size (1) does not match connection size (32) for port 'Z'. The port definition is at: NOT.sv(3).
#    Time: 0 ns  Iteration: 0  Instance: /mux4_test/m4a/mux2b/g6 File: NOT.sv
# ** Error (suppressible): (vsim-3053) mux2.sv(19): Illegal output or inout port connection for port 'Z'.
#    Time: 0 ns  Iteration: 0  Instance: /mux4_test/m4a/mux2c/g6 File: NOT.sv
# ** Warning: (vsim-3015) mux2.sv(19): [PCDPC] - Port size (1) does not match connection size (32) for port 'Z'. The port definition is at: NOT.sv(3).
#    Time: 0 ns  Iteration: 0  Instance: /mux4_test/m4a/mux2c/g6 File: NOT.sv

And here's my attempt in doing it:

For 2:1 mux:

module mux2 (
    input logic d0,          // Data input 0
    input logic d1,          // Data input 1
    input logic sel,         // Select input
    output logic z           // Output
);


logic w1,w2,w3,w4,w5,w6,w7,w8;
NOT # (.Tpdlh(10), .Tpdhl(8)) g1(.Z(w1) , .A(d0));
OR2 # (.Tpdlh(2), .Tpdhl(6)) g4(.Z(w5), .A(w1), .B(w4));
NOT # (.Tpdlh(10), .Tpdhl(8)) g2(.Z(w2) , .A(d1));
OR2 # (.Tpdlh(2), .Tpdhl(6)) g5(.Z(w6), .A(w2), .B(w3));
NOT # (.Tpdlh(10), .Tpdhl(8)) g3(.Z(w3) , .A(w4));
NOT # (.Tpdlh(10), .Tpdhl(8)) g6(.Z(w7) , .A(w5));
NOT # (.Tpdlh(10), .Tpdhl(8)) g7(.Z(w8) , .A(w6));
OR2 # (.Tpdlh(2), .Tpdhl(6)) g8(.Z(z) , .A(w7), .B(w8));


endmodule

for 4:1 mux:

module mux4 (
    input logic d0,          // Data input 0
    input logic d1,          // Data input 1
    input logic d2,          // Data input 2
    input logic d3,          // Data input 3
    input logic [1:0] sel,   // Select input
    output logic z           // Output
);

logic w1,w2;

mux2 mux2a(
.d0(d0),
.d1(d1),
.sel(sel[0]),
.z(w1)
);




mux2 mux2b(
.d2(d0),
.d3(d1),
.sel(sel[0]),
.z(w2)
);



mux2 mux2c(
.d0(w1),
.d1(w2),
.sel(sel[1]),
.z(z)
);


endmodule

Testbench

module mux4_test;
logic d0,d1,d2,d3,sel[1:0], z;



mux4 m4a(
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.sel(sel),
.z(z)
);




initial begin
d0=1'b0;
d1=1'b0;
d2=1'b0;
d3=1'b0;
sel[0]=1'b0;
sel[1]=1'b0;

#20
d0=1'b1;
d1=1'b0;
d2=1'b0;
d3=1'b0;
sel[0]=1'b0;
sel[1]=1'b0;

end 

endmodule

NOT:

module NOT (
    input logic A,
    output logic Z
);

parameter Tpdlh = 1;
parameter Tpdhl = 1;

not #(Tpdlh, Tpdhl) not1 (Z, A);

endmodule

OR:

module OR2 (
    input logic A,
    input logic B,
    output logic Z
);

parameter Tpdlh = 1;
parameter Tpdhl = 1;

or #(Tpdlh, Tpdhl) or1 (Z, A, B);

endmodule