I am creating a voltage-controlled voltage source based on the schematic below:
I vary the control voltage VC and Vs. (VC varies at X axis, Vs as different lines, 0~10 V).
It resulted that VC doesn't seem to be affecting Vo. Is there anything wrong with the design?
It simulates fine in CircuitLab after flipping the orientation of your op-amp inputs around. As you drew it, the feedback loop was unstable, as Kuba pointed out above:
simulate this circuit – Schematic created using CircuitLab
You may click and run the simulation above. Here's the resulting plot:
I would NOT endorse that this is a practical / useful way to build this circuit in real life, but here you go.
I tried the CircuitLab simulator for the first time and I modified the circuit provided by @compumike to use a PMOS for M2. I was unable to save or export the circuit without paying for a subscription, so I took these screenshots:
and the simulation which shows a linear range with gain of 2x:
You can perform a quick check on your op-amp circuit, to see if feedback is positive, which leads to instability, or negative, which yields a linear relationship between input and output.
You need to identify which stages in the entire feedback loop invert. That is, from the op-amp's output, through the various stages in the feedback path, back to its input, and then through the op-amp itself, back to output. So, you need to understand the differences between MOSFET common-source (or BJT common-emitter), and MOSFET common-drain (or BJT common-collector) configurations.
For quick reference, here they are in a very simplistic form:
simulate this circuit – Schematic created using CircuitLab
By "inverting" I mean that a rise in input potential causes a fall in output potential, and vice versa. By "non-inverting" I mean that the output changes in the same direction as the input.
"Followers" like common-drain and common-collector configurations are non-inverting, because their outputs (taken from the transistor's source or emitter) literally follow changes changes in input, with a gain of close to +1.
Common-source or common-emitter configurations, though, are inverting, with negative voltage gain, usually much greater than unity. Something like -100 would be typical.
Now, following your feedback loop from the op-amp's output we have:
The first stage consists of Q3 in a common-source setup. That stage inverts.
Next you have Q2 configured as a source follower, so it does not invert.
Lastly, the op-amp itself takes a fraction of the output from Q2 at its own inverting input, which causes the op-amp's output to move in the opposite direction, another inversion.
Putting all those together in a chain, clearly the combined effect is a non-inversion. Two of the stages invert, cancelling each other's direction-of-change reversal, and the other introduces no direction change. In general, an odd number of inversions always leads to an overall inversion, while an even number does not.
Note: I have not considered phase shifts that may be present due to reactive elements in the loop. Accumulated phase shifts in the vicinity of 180° are equivalent to an inversion. This is a grossly simplified model.
Therefore, in your circuit with an even number of inversions, you have positive feedback, which is unstable. To make it negative, all you have to do is:
Swap the inverting and non-inverting terminals of the op-amp, to make the total number of inversions odd. Then you have negative feedback, with all the consequent linearity and stability.
The W/L ratio for your MOSFETs is much too low. In other words, the transistors are much too small for the current you expect them to conduct. I suggest you replace them with 2n7000s to verify that the circuit works, then try making your MOSFETs bigger (like hundreds of times bigger) until you get enough current.
The common operation of Linear Regulators is that they rely on the load to pull down voltage and a series transistor with low dropout or low Rce or RdsOn to pull up.
The missing clue was VHV, very high voltage. This circuit then begins to make sense as a high voltage linear regulator for very low currents by relying on a high voltage drop for R4,R6 with the same duvide ratios from R1,R3. Vgs must be limited by design of this ratio times your VHV source.
High is a relative number for VHV on pin 8, but "8" rotated is not infinite ;) Several thousand volts may be possible with special HV resistors.
The Op Amp provides the gain to null the between the differential inputs. Since the added output stages invert to create negative feedback it MUST go to the non-inverting input Vin+. Control then is applied to Vin- such that the inputs match when regulated. The Op Amp must have P type inputs in order for the common+mode range to go to 0V. The FET Vds spec must also exceed the VHV specs and power must be limited to a prevent heat loss.
