Verilog code for solving a logic gate has this error: Invalid module instantiation

Question

I was going through a book, and there is this exercise that I need to solve with Verilog. I wrote this code, but it's giving me this error:

main.v:20: syntax error
main.v:20: error: Invalid module instantiation

Any help would be hugely appreciated. Code is:

module Exercise(A,B,C);
  input A,B;
  output C;
  wire w1,w2;
    
  not not1(w1,B);
  or or1(w2,B,w1);
  or or2(C,A,w2);
endmodule

module main;
  reg A,B;
  wire C;
  
  Exercise exer1(C,A,B);
  
  initial 
      begin
      A = 0;
      B = 1;
      #5;
      $display("Result = ",C);
    end
endmodule

toolic · Accepted Answer · 2022-10-04 00:32:22Z

The problem is with the connections to the module instance. You connected a reg to the module output: B in the main module is connected to C in the Exercise module.

You are using connection by order, but you should use connection by name.

Change:

  Exercise exer1(C,A,B);

to:

  Exercise exer1 (.C(C), .A(A), .B(B));

Here is the new main module.

module main;
  reg A,B;
  wire C;
  
    Exercise exer1 (.C(C), .A(A), .B(B));

  initial 
      begin
      A = 0;
      B = 1;
      #5;
      $display("Result = ",C);
    end
endmodule

Your simulator error message is not very specific. You can get more helpful error messages with other simulators which are available on EDA Playground. This link has a complete, runnable code example which proves that the code no longer has a syntax error.

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